State (#144)

* added terra state machine lang alpha

.circleci/config.yml

@@ -14,9 +14,11 @@ jobs:
       - image: circleci/python:3.7.1
     steps:
       - checkout
-      - run: sudo apt-get install luajit verilator
-#      - run: sudo apt-get install luajit flex bison
-#      - run: wget https://www.veripool.org/ftp/verilator-4.012.tgz; tar xvzf verilator*.t*gz;ls;cd verilator-4.012;./configure;make -j2;sudo make install; cd ..;
+#      - run: sudo apt-get install luajit verilator
+      - run: sudo apt-get install luajit
+      - run: sudo apt-get install luajit flex bison
+      - run: wget https://www.veripool.org/ftp/verilator-4.012.tgz; tar xvzf verilator*.t*gz;ls;cd verilator-4.012;./configure;make -j2;sudo make install; cd ..;
+      - run: verilator --version
       - run: cd examples; make verilator
       - run: test -e examples/out/verilator_done.txt || exit
   verilatorSOC:
@@ -69,6 +71,17 @@ jobs:
       - run: sudo ln -s /home/circleci/project/terra-Linux-x86_64-332a506/bin/terra /usr/bin/terra
       - run: cd examples; make terra
       - run: test -e examples/out/terra_done.txt || exit
+  state:
+    docker:
+      - image: circleci/python:3.7.1
+    steps:
+      - checkout
+      - run: sudo apt-get install luajit verilator
+      - run: wget https://github.com/zdevito/terra/releases/download/release-2016-03-25/terra-Linux-x86_64-332a506.zip
+      - run: unzip terra-Linux-x86_64-332a506.zip
+      - run: sudo ln -s /home/circleci/project/terra-Linux-x86_64-332a506/bin/terra /usr/bin/terra
+      - run: cd examples; make state
+      - run: test -e examples/out/state_done.txt || exit
 workflows:
   version: 2
   dostuff:
@@ -79,3 +92,4 @@ workflows:
       - unit
       - terra
       - bjump
+      - state

examples/gold/soc_2in.verilatorSOC.cycles.txt

@@ -1 +1 @@
-1033
+1035

examples/gold/soc_convtest.verilatorSOC.cycles.txt

@@ -1 +1 @@
-7137
+7139

examples/gold/soc_filterseq.verilatorSOC.cycles.txt

@@ -1 +1 @@
-8031
+8033

examples/gold/soc_redu1024.verilatorSOC.cycles.txt

@@ -1 +1 @@
-1043
+1045

examples/gold/soc_redu16384.verilatorSOC.cycles.txt

@@ -1 +1 @@
-16451
+16453

examples/gold/soc_redu32768.verilatorSOC.cycles.txt

@@ -1 +1 @@
-32835
+32837

examples/gold/soc_redu8192.verilatorSOC.cycles.txt

@@ -1 +1 @@
-8259
+8261

examples/gold/soc_regin.verilatorSOC.cycles.txt

@@ -1 +1 @@
-1033
+1035

examples/gold/soc_regout.verilatorSOC.cycles.txt

@@ -1 +1 @@
-8201
+8203

examples/gold/soc_simple.verilatorSOC.cycles.txt

@@ -1 +1 @@
-1033
+1035

examples/gold/soc_simple_uniform.verilatorSOC.cycles.txt

@@ -1 +1 @@
-1033
+1035

examples/gold/soc_tokencounter.verilatorSOC.cycles.txt

@@ -1 +1 @@
-8071
+8073

examples/gold/soc_underflow.verilatorSOC.cycles.txt

@@ -1 +1 @@
-8337
+8339

examples/gold/state_flowcontrol.bmp

@@ -0,0 +1 @@
+pointwise_wide_handshake.bmp

examples/gold/state_flowcontrol.regout.lua

@@ -0,0 +1 @@
+return {}

examples/gold/state_flowcontrol.verilatorSOC.cycles.txt

@@ -0,0 +1 @@
+8203

examples/gold/state_simple.regout.lua

@@ -0,0 +1 @@
+return {}

examples/gold/state_simple.verilatorSOC.cycles.txt

@@ -0,0 +1 @@
+8203

examples/makefile

@@ -10,6 +10,15 @@ VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.correct.txt,$(SRCS_
 VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.regcorrect.txt,$(SRCS_SOC))	
 VERILATOR_SOC += $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.cyclescorrect.txt,$(SRCS_SOC))
 
+SRCS_STATE = state_simple.t state_flowcontrol.t
+
+STATE = $(patsubst %.t,$(BUILDDIR)/%.verilatorSOC.bit,$(SRCS_STATE))
+STATE += $(patsubst %.t,$(BUILDDIR)/%.verilatorSOC.raw,$(SRCS_STATE))
+STATE += $(patsubst %.t,$(BUILDDIR)/%.verilatorSOC.bmp,$(SRCS_STATE))
+STATE += $(patsubst %.t,$(BUILDDIR)/%.verilatorSOC.correct.txt,$(SRCS_STATE))
+STATE += $(patsubst %.t,$(BUILDDIR)/%.verilatorSOC.regcorrect.txt,$(SRCS_STATE))
+STATE += $(patsubst %.t,$(BUILDDIR)/%.verilatorSOC.cyclescorrect.txt,$(SRCS_STATE))	
+
 SRCS_BJUMP = soc_bjump_cache.lua  soc_bjump_cache_nocache.lua
 
 BJUMP = $(patsubst %.lua,$(BUILDDIR)/%.verilatorSOC.bit,$(SRCS_BJUMP))
@@ -272,6 +281,10 @@ bjump: $(BJUMP)
 	touch $(BUILDDIR)/bjump_done.txt
 	date
 
+state: $(STATE)
+	touch $(BUILDDIR)/state_done.txt
+	date
+
 pulpino: $(PULPINO)
 	touch $(BUILDDIR)/pulpino_done.txt
 	date
@@ -317,12 +330,24 @@ $(BUILDDIR)/%.metadata.lua: %.lua
 	mkdir -p $(BUILDDIR)/$*_build
 	- cp $(BUILDDIR)/$*.metadata.lua $(BUILDDIR)/$*_build
 
+$(BUILDDIR)/%.metadata.lua: %.t
+	$(TERRA) $< metadata
+	# keep copy for future reference
+	mkdir -p $(BUILDDIR)/$*_build
+	- cp $(BUILDDIR)/$*.metadata.lua $(BUILDDIR)/$*_build
+
 $(BUILDDIR)/%.v: %.lua
 	$(LUA) $< verilator
 	# keep copy for future reference
 	mkdir -p $(BUILDDIR)/$*_build
 	- cp $(BUILDDIR)/$*.v $(BUILDDIR)/$*_build
 
+$(BUILDDIR)/%.v: %.t
+	$(TERRA) $< verilator
+	# keep copy for future reference
+	mkdir -p $(BUILDDIR)/$*_build
+	- cp $(BUILDDIR)/$*.v $(BUILDDIR)/$*_build
+
 $(BUILDDIR)/%.v.mpsocwrapper.v: $(BUILDDIR)/%.v $(BUILDDIR)/%.metadata.lua
 	$(LUA) ../platform/axi/wrapper.lua $(BUILDDIR)/$*.v $(BUILDDIR)/$*.metadata.lua $@ ../platform/ mpsoc
 

examples/soc_bjump_cache.lua

@@ -32,7 +32,7 @@ local PosToAddr = G.Module{"PosToAddr",ar(u16,2),
 
 local SlowRead = C.compose("SlowRead",SOC.read("1080p.raw",1920*1080,ar(u8,4),noc.read,false),RM.liftHandshake(RM.reduceThroughput(types.uint(32),8)))
 local SlowReadBurst = C.compose("SlowReadBurst",SOC.read("1080p.raw",1920*1080,ar(u8,4*8),noc.read,false),RM.liftHandshake(RM.reduceThroughput(types.uint(32),8)))
-local BurstRead = C.compose("BurstRead",G.HS{G.SerSeq{8}},SlowReadBurst)
+local SlowBurstReadSer = C.compose("SlowBurstReadSer",G.HS{G.SerSeq{8}},SlowReadBurst)
 
 local CachedReadModule = G.Module{ "CachedReadModule", R.HandshakeTrigger,
   function(i)
@@ -46,7 +46,7 @@ local CachedReadModule = G.Module{ "CachedReadModule", R.HandshakeTrigger,
     if NOCACHE then
       stencil = G.Map{SlowRead}(addr)
     else
-      stencil = G.Map{bjump.AXICachedRead(ar(u(8),4),8,8,BurstRead)}(addr)
+      stencil = G.Map{bjump.AXICachedRead(ar(u(8),4),8,8,SlowBurstReadSer)}(addr)
     end
 
     stencil = G.Map{G.HS{G.Deser{8}}}(stencil)

examples/state_flowcontrol.t

@@ -0,0 +1,44 @@
+local types = require "types"
+local C = require "examplescommon"
+local R = require "rigel"
+local harness = require "harnessSOC"
+local Zynq = require "zynq"
+local SOC = require "soc"
+local SDF = require "sdf"
+local G = require "generators"
+local RM = require "modules"
+local AXI = require "axi"
+import "state"
+
+
+--function FlowControl(readFn)
+--  return 
+--end
+
+noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+noc.extern=true
+local regs = SOC.axiRegs({},SDF{1,128*64},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
+
+print("INST",noc.read)
+
+-- only issue requests for which we have pre-allocated storage
+state FlowControl(I:AXI.ReadAddress64,O:AXI.ReadData64)
+  fifo:RM.fifo(AXI.ReadDataTuple(64),8,nil,nil,nil,nil,nil,true,nil,true)
+--1
+  while R.c(true,types.bool()) do
+    if G.LT{7}(fifo:size()) then
+      [fifo:store(noc.read(I))]
+    else
+      [C.Stall(AXI.ReadAddressTuple,true)(I)]
+      [fifo:store(noc:read(C.Invalid(AXI.ReadAddressTuple,true)()))]
+    end
+    yield fifo:load() -- 2
+  end
+end
+
+--l-ocal FC = FlowControl(noc.read)
+--print(FlowControl)
+--print(FlowControl:toVerilog())
+
+
+harness({regs.start, G.AXIReadBurst{ "frame_128.raw", {128,64}, types.u(8), 0, FlowControl }, G.HS{G.Map{G.Add{200}}}, G.AXIWriteBurst{"out/state_flowcontrol",noc.write}, regs.done},nil,{regs})

examples/state_simple.t

@@ -0,0 +1,46 @@
+local types = require "types"
+local C = require "examplescommon"
+local R = require "rigel"
+local harness = require "harnessSOC"
+local Zynq = require "zynq"
+local SOC = require "soc"
+local SDF = require "sdf"
+local G = require "generators"
+import "state"
+
+state StateExample(I:types.uint(8),O:types.uint(8))
+--1
+--yield R.c(8,types.u8)
+  while R.c("mytrue",true,types.bool()) do
+    if C.GTConst(types.uint(8),16)(I) then
+      yield R.c(255,types.u8) --2
+
+      if C.GTConst(types.uint(8),128)(I) then
+        yield R.c(128,types.u8) --3
+      else
+        yield R.c(64,types.u8) --4 
+      end
+    else
+      yield R.c(0,types.u8) --5
+
+      if C.GTConst(types.uint(8),8)(I) then
+        yield R.c(16,types.u8) --6
+      else
+        yield R.c(8,types.u8) --7
+      end
+
+    end
+  end
+end
+
+--print("COUNTER",StateExample)
+
+--print("counter",StateExample:toVerilog())
+
+noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+noc.extern=true
+local regs = SOC.axiRegs({},SDF{1,128*64},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
+
+harness({regs.start, G.AXIReadBurst{ "frame_128.raw", {128,64}, types.u(8), 0, noc.read }, G.Map{G.HS{StateExample}}, G.Map{G.FIFO{128}}, G.AXIWriteBurst{"out/state_simple",noc.write}, regs.done},nil,{regs})
+
+--harness({regs.start, G.AXIReadBurst{ "frame_128.raw", {128,64}, types.u(8), 0, noc.read }, G.Map{G.HS{C.plusConst(types.u8,0)}}, G.AXIWriteBurst{"out/stateex",noc.write}, regs.done},nil,{regs})

modules/axi.lua

@@ -31,15 +31,20 @@ AXI.ReadAddressIdx={araddr=0,arlen=1,arsize=2,arburst=3,arid=4,arprot=5,arcache=
 AXI.ReadAddressVSelect = {arvalid="["..tostring(types.extractData(AXI.ReadAddress):verilogBits()).."]"}
 for k,v in pairs(AXI.ReadAddressIdx) do AXI.ReadAddressVSelect[k] = vrange(types.extractData(AXI.ReadAddress),AXI.ReadAddressIdx[k],0) end
 
+AXI.ReadDataTuple = J.memoize(function(bits)
+  return types.tuple{
+    types.bits(bits), -- RDATA
+    types.bool(), -- RLAST
+    types.bits(2), -- RRESP
+    types.bits(12), -- RID
+  }
+end)
+
 AXI.ReadData = J.memoize(function(bits)
     assert(type(bits)=="number")
-    return types.HandshakeVR(types.tuple{
-                             types.bits(bits), -- RDATA
-                             types.bool(), -- RLAST
-                             types.bits(2), -- RRESP
-                             types.bits(12), -- RID
-    })
+    return types.HandshakeVR(AXI.ReadDataTuple(bits))
 end)
+
 AXI.ReadData64 = AXI.ReadData(64)
 AXI.ReadData32 = AXI.ReadData(32)
 

modules/bjump.lua

@@ -238,7 +238,7 @@ endmodule
  );
     ]=]
 
-    s.verilog = table.concat(vstr,"\n")
+    s:verilog(table.concat(vstr,"\n"))
     return s
   end