fix clocking issue with BUFG_PS

jameshegarty · Jan 25, 2018 · 5c0bca0 · 5c0bca0
1 parent 3ce729b
commit 5c0bca0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/platform/axi/mpsoc.v b/platform/axi/mpsoc.v
@@ -9,7 +9,7 @@ module stage
   wire ARESETN;
 
   //AA change here: removed buffer for now
-  BUFG bufg(.I(fclk[0]),.O(FCLK0)); 
+  BUFG_PS bufg(.I(fclk[0]),.O(FCLK0));
   //assign FCLK0 = fclk[0];  
 
   assign ARESETN = 1'b1; //fclkresetn[0];