progress on tests

jameshegarty · Feb 23, 2019 · 81eb310 · 81eb310
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commit 81eb310
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Showing 11 changed files with 129 additions and 70 deletions.
diff --git a/examples/soc_2in.lua b/examples/soc_2in.lua
@@ -7,18 +7,21 @@ local RM = require "modules"
 local G = require "generators"
 require "types".export()
 local SDF = require "sdf"
+local Zynq = require "zynq"
 
-regs = SOC.axiRegs({},SDF{1,1024}):instantiate()
+noc = Zynq.SimpleNOC(2):instantiate("ZynqNOC")
+noc.extern=true
+regs = SOC.axiRegs({},SDF{1,1024},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate()
 
 local inp = R.input(R.HandshakeTrigger)
 local inp0, inp1 = RS.fanOut{input=inp,branches=2}
-local a = SOC.readBurst("frame_128.raw",128,64,u(8),8)(inp0)
-local bb = SOC.readBurst("frame_128_inv.raw",128,64,u(8),8)(inp1)
+local a = SOC.readBurst("frame_128.raw",128,64,u(8),8,nil,nil,noc.read)(inp0)
+local bb = SOC.readBurst("frame_128_inv.raw",128,64,u(8),8,nil,nil,noc.read1)(inp1)
 local out = G.FanIn{true}(a,bb)
 out = RS.HS(RM.SoAtoAoS(8,1,{u(8),u(8)}))(out)
 out = RS.HS(RM.map(C.sum(u(8),u(8),u(8)),8))(out)
 --out = RS.HS(C.cast(ar(u(8),8),b(64)))(out)
-out = SOC.writeBurst("out/soc_2in",128,64,u(8),8)(out)
+out = SOC.writeBurst("out/soc_2in",128,64,u(8),8,nil,noc.write)(out)
 
 local fn = RM.lambda("FN",inp,out)
-harness{regs.start,fn,regs.done}
+harness({regs.start,fn,regs.done},nil,{regs})
diff --git a/examples/soc_convgen.lua b/examples/soc_convgen.lua
@@ -7,14 +7,17 @@ local C = require "examplescommon"
 local SDF = require "sdf"
 require "generators".export()
 require "types".export()
+local Zynq = require "zynq"
 
 local ConvWidth = 4
 local ConvRadius = ConvWidth/2
 
 inSize = { 1920, 1080 }
 padSize = { 1920+16, 1080+3 }
 
-regs = SOC.axiRegs({},SDF{1,padSize[1]*padSize[2]}):instantiate()
+noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+noc.extern=true
+regs = SOC.axiRegs({},SDF{1,padSize[1]*padSize[2]},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 local conv = Module{ ar(u(8),ConvWidth,ConvWidth),
 function(inp)
@@ -29,13 +32,13 @@ function(inp)
   return RemoveMSBs{24}(Rshift{8}(res))
 end}
 
-harness{
+harness({
   regs.start,
-  SOC.readBurst("1080p.raw",1920,1080,u(8),1),
+  SOC.readBurst("1080p.raw",1920,1080,u(8),1,nil,nil,noc.read),
   HS{Pad{inSize,1,{8,8,2,1}}},
 --  RS.HS(C.print(ar(u(8),1))),
   HS{Linebuffer{padSize,1,{3,0,3,0}}},
   HS{Map{conv}},
   HS{CropSeq{padSize,1,{9,7,3,0}}},
-  SOC.writeBurst("out/soc_convgen",1920,1080,u(8),1),
-  regs.done}
+  SOC.writeBurst("out/soc_convgen",1920,1080,u(8),1,nil,noc.write),
+  regs.done},nil,{regs})
diff --git a/examples/soc_convgenTaps.lua b/examples/soc_convgenTaps.lua
@@ -7,35 +7,39 @@ local C = require "examplescommon"
 require "generators".export()
 require "types".export()
 local SDF = require "sdf"
+local Zynq = require "zynq"
 
 local ConvWidth = 4
 local ConvRadius = ConvWidth/2
 
 inSize = { 1920, 1080 }
 padSize = { 1920+16, 1080+3 }
 
+noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+noc.extern=true
+
 regs = SOC.axiRegs({
   coeffs={ar(u(32),ConvWidth,ConvWidth),
           {4, 14, 14,  4,
            14, 32, 32, 14,
            14, 32, 32, 14,
-           4, 14, 14,  4}}},SDF{1,padSize[1]*padSize[2]}):instantiate()
+           4, 14, 14,  4}}},SDF{1,padSize[1]*padSize[2]},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 local conv = Module{ ar(u(8),ConvWidth,ConvWidth),
 function(inp)
   inp = Map{AddMSBs{24}}(inp)
-  local z = Zip(inp,regs.module.coeffs)
+  local z = Zip(inp,regs.coeffs())
   local out = Map{Mul}(z)
   local res = Reduce{Add}(out)
   return RemoveMSBs{24}(Rshift{8}(res))
 end}
 
-harness{
+harness({
   regs.start,
-  SOC.readBurst("1080p.raw",1920,1080,u(8),1),
+  SOC.readBurst("1080p.raw",1920,1080,u(8),1,nil,nil,noc.read),
   HS{Pad{inSize,1,{8,8,2,1}}},
   HS{Linebuffer{padSize,1,{3,0,3,0}}},
   HS{Map{conv}},
   HS{CropSeq{padSize,1,{9,7,3,0}}},
-  SOC.writeBurst("out/soc_convgenTaps",1920,1080,u(8),1),
-  regs.done}
+  SOC.writeBurst("out/soc_convgenTaps",1920,1080,u(8),1,nil,noc.write),
+  regs.done},nil,{regs})
diff --git a/examples/soc_flip.lua b/examples/soc_flip.lua
@@ -5,9 +5,12 @@ local harness = require "harnessSOC"
 local SOC = require "soc"
 local C = require "examplescommon"
 local SDF = require "sdf"
+local Zynq = require "zynq"
 require "types".export()
 
-regs = SOC.axiRegs({},SDF{1,1024}):instantiate()
+noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
+noc.extern=true
+regs = SOC.axiRegs({},SDF{1,1024},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate("regs")
 
 local W,H = 128,64
 
@@ -18,11 +21,11 @@ addrGen = Module{function(inp)
   return Add(resx,resy)
 end}
 
-harness{
+harness({
   regs.start,
   C.triggerUp( (W*H)/8 ),
   HS{PosSeq{{W/8,H},1}},
   HS{addrGen},
-  SOC.read("frame_128.raw",128*64,ar(u(8),8)),
-  SOC.writeBurst("out/soc_flip",128,64,u(8),8),
-  regs.done}
+  SOC.read("frame_128.raw",128*64,ar(u(8),8,nil,nil,noc.read)),
+  SOC.writeBurst("out/soc_flip",128,64,u(8),8,nil,noc.write),
+  regs.done},nil,{regs})
diff --git a/examples/soc_simple.lua b/examples/soc_simple.lua
@@ -9,7 +9,7 @@ types.export()
 local SDF = require "sdf"
 local Zynq = require "zynq"
 
-noc = Zynq.SimpleNOC:instantiate("ZynqNOC")
+noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
 noc.extern=true
 regs = SOC.axiRegs({},SDF{1,1024},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink):instantiate()
 

diff --git a/examples/soc_simple_uniform.lua b/examples/soc_simple_uniform.lua
@@ -9,7 +9,7 @@ local SDF = require "sdf"
 local Zynq = require "zynq"
 types.export()
 
-noc = Zynq.SimpleNOC:instantiate("ZynqNOC")
+noc = Zynq.SimpleNOC():instantiate("ZynqNOC")
 noc.extern=true
 Regs = SOC.axiRegs({readAddress={u(32),0x30008000},writeAddress={u(32),0x30008000+(128*64)}},SDF{1,128*64},noc.readSource,noc.readSink,noc.writeSource,noc.writeSink)
 regs = Regs:instantiate("regs")

diff --git a/modules/examplescommon.lua b/modules/examplescommon.lua
@@ -349,7 +349,7 @@ C.addMSBs = memoize(function(A,bits)
     J.err( A:isUint() or A:isInt(), "generators.addMSBs: type should be int or uint, but is: "..tostring(A) )
   end
 
-  local mod = RM.lift(J.sanitize("generators_addMSBs_"..tostring(bits).."_"..tostring(A)), A,otype,nil,
+  local mod = RM.lift(J.sanitize("generators_addMSBs_"..tostring(bits).."_"..tostring(A)), A,otype,0,
                       function(inp) return S.cast(inp,otype) end)
   return mod
 end)
@@ -370,7 +370,7 @@ C.removeMSBs = memoize(function(A,bits)
     J.err( A:isUint() or A:isInt(), "generators.removeMSBs: type should be int or uint, but is: "..tostring(A) )
   end
 
-  local mod = RM.lift(J.sanitize("generators_removeMSBs_"..tostring(bits).."_"..tostring(A)), A,otype,nil,
+  local mod = RM.lift(J.sanitize("generators_removeMSBs_"..tostring(bits).."_"..tostring(A)), A,otype, 0,
                       function(inp) return S.cast(inp,otype) end)
   return mod
 end)

diff --git a/modules/soc.lua b/modules/soc.lua
@@ -842,6 +842,7 @@ SOC.axiBurstReadN = J.memoize(function(filename,Nbytes_orig,port,address_orig,re
 
   local ModuleName = J.sanitize("DRAMReader_"..tostring(Nbytes_orig).."_"..tostring(port).."_"..tostring(address_orig))
 
+  local RPORT = readFn.instance.name.."_"..readFn.functionName
   local vstr = [=[module ]=]..ModuleName..[=[_inner(
     //AXI port
     input wire ACLK,
@@ -1011,11 +1012,11 @@ module ]=]..ModuleName..[=[(
   input wire CLK,
   input wire reset,
 
-  output wire [55:0] ZynqNOC_read_input,
-  input wire [79:0] ZynqNOC_read,
+  output wire [55:0] ]=]..RPORT..[=[_input,
+  input wire [79:0] ]=]..RPORT..[=[,
 
-  output wire ZynqNOC_read_ready_downstream,
-  input wire ZynqNOC_read_ready,
+  output wire ]=]..RPORT..[=[_ready_downstream,
+  input wire ]=]..RPORT..[=[_ready,
 
   ]=]..address:toVerilogPortList()..[=[
   ]=]..Nbytes:toVerilogPortList()..[=[
@@ -1038,16 +1039,16 @@ parameter INSTANCE_NAME="inst";
     ]=]..address:toVerilogPassthrough()..[=[
     ]=]..Nbytes:toVerilogPassthrough()..[=[
 
-    .IP_MAXI_ARADDR({ZynqNOC_read_input[55],ZynqNOC_read_input[31:0]}),
-    .IP_MAXI_ARADDR_ready(ZynqNOC_read_ready),
-    .IP_MAXI_ARLEN(ZynqNOC_read_input[35:32]),
-    .IP_MAXI_ARSIZE(ZynqNOC_read_input[37:36]),
-    .IP_MAXI_ARBURST(ZynqNOC_read_input[39:38]),
+    .IP_MAXI_ARADDR({]=]..RPORT..[=[_input[55],]=]..RPORT..[=[_input[31:0]}),
+    .IP_MAXI_ARADDR_ready(]=]..RPORT..[=[_ready),
+    .IP_MAXI_ARLEN(]=]..RPORT..[=[_input[35:32]),
+    .IP_MAXI_ARSIZE(]=]..RPORT..[=[_input[37:36]),
+    .IP_MAXI_ARBURST(]=]..RPORT..[=[_input[39:38]),
 
-    .IP_MAXI_RDATA({ZynqNOC_read[79],ZynqNOC_read[63:0]}),
-    .IP_MAXI_RDATA_ready(ZynqNOC_read_ready_downstream),
-    .IP_MAXI_RLAST(ZynqNOC_read[64]),
-    .IP_MAXI_RRESP(ZynqNOC_read[66:65])
+    .IP_MAXI_RDATA({]=]..RPORT..[=[[79],]=]..RPORT..[=[[63:0]}),
+    .IP_MAXI_RDATA_ready(]=]..RPORT..[=[_ready_downstream),
+    .IP_MAXI_RLAST(]=]..RPORT..[=[[64]),
+    .IP_MAXI_RRESP(]=]..RPORT..[=[[66:65])
 );
 
 endmodule
@@ -1809,7 +1810,7 @@ SOC.writeBurst = J.memoize(function( filename, W, H, ty, V, framed, writeFn, X)
   J.err( V==nil or type(V)=="number", "writeBurst: V must be number or nil")
   if V==nil then V=1 end
   if framed==nil then framed=false end
-  J.err( type(framed)=="boolean","writeBurst: framed must be boolean")
+  J.err( type(framed)=="boolean","writeBurst: framed must be boolean, but is: "..tostring(framed))
   J.err( R.isFunction(writeFn), "writeBurst: writeFn should be rigel function, but is: "..tostring(writeFn))
   J.err(X==nil, "writeBurst: too many arguments")
 

diff --git a/modules/zynq.lua b/modules/zynq.lua
@@ -51,16 +51,29 @@ end)
 
 -- for regs: issueRead, readResponse, issueWrite, writeResponse
 -- for IP DMAs: read, write
-local SimpleNOCFns = {}
-SimpleNOCFns.readSource = R.newFunction{name="ReadSource",inputType=types.null(),outputType=AXI.ReadAddress,sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
-SimpleNOCFns.readSink = R.newFunction{name="ReadSink",inputType=AXI.ReadData(32),outputType=types.null(),sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
 
-SimpleNOCFns.writeSource = R.newFunction{name="WriteSource",inputType=types.null(),outputType=AXI.WriteIssue(32),sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
-SimpleNOCFns.writeSink = R.newFunction{name="WriteSink",inputType=AXI.WriteResponse(32),outputType=types.null(),sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
 
-SimpleNOCFns.read = R.newFunction{name="Read",inputType=AXI.ReadAddress,outputType=AXI.ReadData(64),sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
-SimpleNOCFns.write = R.newFunction{name="Write",inputType=AXI.WriteIssue(64), outputType=AXI.WriteResponse(64), sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
-Zynq.SimpleNOC = R.newModule("Zynq_NOC",SimpleNOCFns,false,nil,nil)
-Zynq.SimpleNOC.makeSystolic = function() return C.automaticSystolicStub(Zynq.SimpleNOC) end
+Zynq.SimpleNOC = function(readPorts,writePorts)
+  if readPorts==nil then readPorts=1 end
+  if writePorts==nil then writePorts=1 end
+
+  local SimpleNOCFns = {}
+  SimpleNOCFns.readSource = R.newFunction{name="ReadSource",inputType=types.null(),outputType=AXI.ReadAddress,sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
+  SimpleNOCFns.readSink = R.newFunction{name="ReadSink",inputType=AXI.ReadData(32),outputType=types.null(),sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
+
+  SimpleNOCFns.writeSource = R.newFunction{name="WriteSource",inputType=types.null(),outputType=AXI.WriteIssue(32),sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
+  SimpleNOCFns.writeSink = R.newFunction{name="WriteSink",inputType=AXI.WriteResponse(32),outputType=types.null(),sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
+
+  for i=1,readPorts do
+    SimpleNOCFns["read"..J.sel(i==1,"",tostring(i-1))] = R.newFunction{name="Read",inputType=AXI.ReadAddress,outputType=AXI.ReadData(64),sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
+  end
+
+  SimpleNOCFns.write = R.newFunction{name="Write",inputType=AXI.WriteIssue(64), outputType=AXI.WriteResponse(64), sdfInput=SDF{1,1},sdfOutput=SDF{1,1}, stateful=false}
+
+  local NOC = R.newModule("Zynq_NOC",SimpleNOCFns,false,nil,nil)
+  NOC.makeSystolic = function() return C.automaticSystolicStub(NOC) end
+
+  return NOC
+end
 
 return Zynq
diff --git a/platform/verilatorSOC/verilator_wrapper.lua b/platform/verilatorSOC/verilator_wrapper.lua
@@ -19,6 +19,23 @@ function assnRigelToExt(vtab,dest,src)
   return str
 end
 
+local READ_PORTS = ""
+
+for i=1,2 do
+  local PORT = "ZynqNOC_read"
+  if i>1 then PORT=PORT..tostring(i-1) end
+
+  READ_PORTS = READ_PORTS..[[wire         ]]..PORT..[[_ready_downstream;
+   assign MAXI]]..(i-1)..[[_RREADY = ]]..PORT..[[_ready_downstream;
+   wire   ]]..PORT..[[_ready;
+   assign ]]..PORT..[[_ready = MAXI]]..(i-1)..[[_ARREADY;
+   wire [55:0] ]]..PORT..[[_input; // read request
+   ]]..assnRigelToExt(AXI.ReadAddressVSelect,"MAXI"..(i-1).."_",PORT.."_input")..[[
+   wire [79:0] ]]..PORT..[[;    // read response
+   assign ]]..PORT..[[ = {MAXI]]..(i-1)..[[_RVALID,]]..assnExtToRigel(AXI.ReadDataIdx,"MAXI"..(i-1).."_")..[[};
+]]
+end
+
 print([[module VerilatorWrapper(
   input         IP_CLK,
   input         IP_ARESET_N,
@@ -94,6 +111,9 @@ print([[module VerilatorWrapper(
     output        MAXI1_ARVALID,
     input         MAXI1_ARREADY,
     input [63:0]  MAXI1_RDATA,
+    input [11:0]  MAXI1_RID,
+    output [2:0]  MAXI1_ARPROT,
+    output [11:0] MAXI1_ARID,
     input         MAXI1_RVALID,
     output        MAXI1_RREADY,
     input [1:0]   MAXI1_RRESP,
@@ -128,14 +148,6 @@ print([[module VerilatorWrapper(
    assign SAXI0_ARREADY = ZynqNOC_readSource_ready_downstream;
    wire         ZynqNOC_writeSink_ready;
    assign ZynqNOC_writeSink_ready= SAXI0_BREADY;
-   wire         ZynqNOC_read_ready_downstream;
-   assign MAXI0_RREADY = ZynqNOC_read_ready_downstream;
-   wire   ZynqNOC_read_ready;
-   assign ZynqNOC_read_ready = MAXI0_ARREADY;
-   wire [55:0] ZynqNOC_read_input; // read request
-   ]]..assnRigelToExt(AXI.ReadAddressVSelect,"MAXI0_","ZynqNOC_read_input")..[[
-   wire [79:0] ZynqNOC_read;    // read response
-   assign ZynqNOC_read = {MAXI0_RVALID,]]..assnExtToRigel(AXI.ReadDataIdx,"MAXI0_")..[[};
    wire ZynqNOC_write_ready_downstream;  
    assign MAXI0_BREADY = ZynqNOC_write_ready_downstream;
    wire [1:0] ZynqNOC_write_ready;  
@@ -154,6 +166,8 @@ print([[module VerilatorWrapper(
    wire [47:0] ZynqNOC_readSink_input;  // slave read response
    ]]..assnRigelToExt(AXI.ReadDataVSelect(32),"SAXI0_","ZynqNOC_readSink_input")..[[
 
+   ]]..READ_PORTS..[[
+
    Top top(.CLK(IP_CLK), .reset(~IP_ARESET_N), .*);
 
 endmodule]])
diff --git a/platform/verilatorSOC/verilator_wrapper.sv b/platform/verilatorSOC/verilator_wrapper.sv
@@ -73,6 +73,9 @@ module VerilatorWrapper(
     output        MAXI1_ARVALID,
     input         MAXI1_ARREADY,
     input [63:0]  MAXI1_RDATA,
+    input [11:0]  MAXI1_RID,
+    output [2:0]  MAXI1_ARPROT,
+    output [11:0] MAXI1_ARID,
     input         MAXI1_RVALID,
     output        MAXI1_RREADY,
     input [1:0]   MAXI1_RRESP,
@@ -117,20 +120,6 @@ assign MAXI0_AWLEN = ZynqNOC_write_input[35:32];
    assign SAXI0_ARREADY = ZynqNOC_readSource_ready_downstream;
    wire         ZynqNOC_writeSink_ready;
    assign ZynqNOC_writeSink_ready= SAXI0_BREADY;
-   wire         ZynqNOC_read_ready_downstream;
-   assign MAXI0_RREADY = ZynqNOC_read_ready_downstream;
-   wire   ZynqNOC_read_ready;
-   assign ZynqNOC_read_ready = MAXI0_ARREADY;
-   wire [55:0] ZynqNOC_read_input; // read request
-   assign MAXI0_ARLEN = ZynqNOC_read_input[35:32];
-assign MAXI0_ARADDR = ZynqNOC_read_input[31:0];
-assign MAXI0_ARPROT = ZynqNOC_read_input[54:52];
-assign MAXI0_ARVALID = ZynqNOC_read_input[55];
-assign MAXI0_ARID = ZynqNOC_read_input[51:40];
-assign MAXI0_ARSIZE = ZynqNOC_read_input[37:36];
-assign MAXI0_ARBURST = ZynqNOC_read_input[39:38];
-   wire [79:0] ZynqNOC_read;    // read response
-   assign ZynqNOC_read = {MAXI0_RVALID,MAXI0_RID,MAXI0_RRESP,MAXI0_RLAST,MAXI0_RDATA};
    wire ZynqNOC_write_ready_downstream;  
    assign MAXI0_BREADY = ZynqNOC_write_ready_downstream;
    wire [1:0] ZynqNOC_write_ready;  
@@ -155,6 +144,35 @@ assign SAXI0_RDATA = ZynqNOC_readSink_input[31:0];
 assign SAXI0_RRESP = ZynqNOC_readSink_input[34:33];
 assign SAXI0_RID = ZynqNOC_readSink_input[46:35];
 
+   wire         ZynqNOC_read_ready_downstream;
+   assign MAXI0_RREADY = ZynqNOC_read_ready_downstream;
+   wire   ZynqNOC_read_ready;
+   assign ZynqNOC_read_ready = MAXI0_ARREADY;
+   wire [55:0] ZynqNOC_read_input; // read request
+   assign MAXI0_ARLEN = ZynqNOC_read_input[35:32];
+assign MAXI0_ARADDR = ZynqNOC_read_input[31:0];
+assign MAXI0_ARPROT = ZynqNOC_read_input[54:52];
+assign MAXI0_ARVALID = ZynqNOC_read_input[55];
+assign MAXI0_ARID = ZynqNOC_read_input[51:40];
+assign MAXI0_ARSIZE = ZynqNOC_read_input[37:36];
+assign MAXI0_ARBURST = ZynqNOC_read_input[39:38];
+   wire [79:0] ZynqNOC_read;    // read response
+   assign ZynqNOC_read = {MAXI0_RVALID,MAXI0_RID,MAXI0_RRESP,MAXI0_RLAST,MAXI0_RDATA};
+wire         ZynqNOC_read1_ready_downstream;
+   assign MAXI1_RREADY = ZynqNOC_read1_ready_downstream;
+   wire   ZynqNOC_read1_ready;
+   assign ZynqNOC_read1_ready = MAXI1_ARREADY;
+   wire [55:0] ZynqNOC_read1_input; // read request
+   assign MAXI1_ARLEN = ZynqNOC_read1_input[35:32];
+assign MAXI1_ARADDR = ZynqNOC_read1_input[31:0];
+assign MAXI1_ARPROT = ZynqNOC_read1_input[54:52];
+assign MAXI1_ARVALID = ZynqNOC_read1_input[55];
+assign MAXI1_ARID = ZynqNOC_read1_input[51:40];
+assign MAXI1_ARSIZE = ZynqNOC_read1_input[37:36];
+assign MAXI1_ARBURST = ZynqNOC_read1_input[39:38];
+   wire [79:0] ZynqNOC_read1;    // read response
+   assign ZynqNOC_read1 = {MAXI1_RVALID,MAXI1_RID,MAXI1_RRESP,MAXI1_RLAST,MAXI1_RDATA};
+
    Top top(.CLK(IP_CLK), .reset(~IP_ARESET_N), .*);
 
 endmodule