circlecifix

jameshegarty · Apr 18, 2019 · aaed7c1 · aaed7c1
1 parent 3c6a68e
commit aaed7c1
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Showing 2 changed files with 5 additions and 4 deletions.
diff --git a/.circleci/config.yml b/.circleci/config.yml
@@ -14,9 +14,10 @@ jobs:
       - image: circleci/python:3.7.1
     steps:
       - checkout
-      - run: sudo apt-get install luajit verilator
-#      - run: sudo apt-get install luajit flex bison
-#      - run: wget https://www.veripool.org/ftp/verilator-4.012.tgz; tar xvzf verilator*.t*gz;ls;cd verilator-4.012;./configure;make -j2;sudo make install; cd ..;
+#      - run: sudo apt-get install luajit verilator
+      - run: sudo apt-get install luajit
+      - run: sudo apt-get install luajit flex bison
+      - run: wget https://www.veripool.org/ftp/verilator-4.012.tgz; tar xvzf verilator*.t*gz;ls;cd verilator-4.012;./configure;make -j2;sudo make install; cd ..;
       - run: verilator --version
       - run: cd examples; make verilator
       - run: test -e examples/out/verilator_done.txt || exit

diff --git a/platform/verilatorSOC/compile b/platform/verilatorSOC/compile
@@ -34,6 +34,6 @@ RAMFILE=$(exec luajit $DIR/../../misc/extractMetadata.lua $METADATA_FILE ramFile
 TAPBITS=$(exec luajit $DIR/../../misc/extractMetadata.lua $METADATA_FILE tapBits)
 
 #-Wno-UNOPTFLAT surpresses circular loop errors... we should probably work to not have to enable this
-verilator -cc -Mdir $BUILDDIR $VERILOG_FILE $DIR/../verilator/RAM128X1D.v $DIR/../verilator/RAMB16_S36_S36.v $DIR/../verilator/RAMB16_S18_S18.v $DIR/../verilator/RAMB16_S9_S9.v $DIR/../verilator/RAMB16_S4_S4.v $DIR/../verilator/RAMB16_RIGEL.v $DIR/verilator_wrapper.sv --top-module VerilatorWrapper
+verilator -Wno-UNOPTFLAT -cc -Mdir $BUILDDIR $VERILOG_FILE $DIR/../verilator/RAM128X1D.v $DIR/../verilator/RAMB16_S36_S36.v $DIR/../verilator/RAMB16_S18_S18.v $DIR/../verilator/RAMB16_S9_S9.v $DIR/../verilator/RAMB16_S4_S4.v $DIR/../verilator/RAMB16_RIGEL.v $DIR/verilator_wrapper.sv --top-module VerilatorWrapper
 make -C $BUILDDIR -f V$TOP.mk
 g++ ${VERILATOR_CFLAGS} -I. -DHARNESS=$HARNESS -DINBPP=$INBPP -DRAMBITS=$RAMBITS -DRAMFILE="\"$RAMFILE\"" -DTAPBITS=$TAPBITS -DVERILATORCLASS="V${TOP}" -DVERILATORFILE="\"${BUILDDIR}/V${TOP}.h\"" ${VERILATOR_INCLUDE}/verilated.cpp $DIR/harness.cpp $BUILDDIR/V${TOP}__ALL.a -o $OUTFILE