Skip to content

Commit

Permalink
Documentation for storage subpackage (#20)
Browse files Browse the repository at this point in the history 
* Finished schematics for storage classes

* Finished documentation for flip-flops and registers

* Finished docs for SIPO and PISO
  • Loading branch information
@jamesjiang52
jamesjiang52 committed Oct 24, 2018
1 parent 4c7889e commit 705c6e7
Show file tree
Hide file tree
Showing 94 changed files with 3,480 additions and 315 deletions.
2 changes: 1 addition & 1 deletion LICENSE
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
MIT License

Copyright (c) [year] [fullname]
Copyright (c) 2018 James Jiang

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
Expand Down
6 changes: 3 additions & 3 deletions README.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,23 +46,23 @@ Interacting with it in a Python session::
In [2]: b.value = 0
In [3]: sum.value
In [3]: sum_.value
Out[3]: 0
In [4]: carry_out.value
Out[4]: 0
In [5]: a.value = 1
In [6]: sum.value
In [6]: sum_.value
Out[6]: 1
In [7]: carry_out.value
Out[7]: 0
In [8]: b.value = 1
In [9]: sum.value
In [9]: sum_.value
Out[9]: 0
In [10]: carry_out.value
Expand Down
2 changes: 0 additions & 2 deletions bitwise/signal/__init__.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,4 @@
from .ENC import *
from .MUX import *
from .INV_CTRL import *
from .PISO import *
from .SIPO import *
from .SSD import *
231 changes: 98 additions & 133 deletions bitwise/storage/FLOP.py
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,4 @@
"""
This module defines classes that simulate primitive storage elements, namely
1-bit latches and 1-bit flip-flops. Latches are level-sensitive, changing their
value according to the value of a clock input, while flip-flops are edge-
sensitive, changing their value according to edges of a clock input.
The following classes are defined:
SRLatch
GatedSRLatch
Expand All @@ -24,38 +19,32 @@


class SRLatch:
"""
This class simulates an SR latch, which has two inputs and two outputs:
________
set ----| |---- output
reset ----|________|---- output_not
If set is 1 and reset is 0, output and output_not are 1 and 0,
respectively. If set is 0 and reset is 1, output and output_not are 0 and
1, respectively. If both set and reset are 0, output and output_not hold
their current values. The input where both set and reset are 1 is not used.
"""Construct a new SR latch.
Args:
set_: An object of type Wire. The set input to the latch.
reset: An object of type Wire. The reset input to the latch.
output: An object of type Wire. The output of the latch. Takes on the
value of 1 if the value of set is 1 and the value of 0 if the value
of reset is 1.
output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, set_, reset, output, output_not):
gate.NORGate2(set_, output, output_not)
gate.NORGate2(reset, output_not, output)


class GatedSRLatch:
"""
This class simulates a gated SR latch, which has three inputs, including a
clock, and two outputs:
________
set ----| |---- output
reset ----| |---- output_not
clock ----|________|
If clock is 0, output and output_not hold their current values, regardless
of the set and reset inputs. If clock is 1 and set and reset are 1 and 0,
respectively, output and output_not are 1 and 0, respectively. If clock is
1 and set and reset are 1 and 0, respectively, output and output_not are 0
and 1, respectively. If clock is 1 and both set and reset are 0, output and
output_not hold their current values. The input where both set and reset
are 1 is not used.
"""Construct a new gated SR latch.
Args:
set_: An object of type Wire. The set input to the latch.
reset: An object of type Wire. The reset input to the latch.
clock: An object of type Wire. The clock input to the latch.
output: An object of type Wire. The output of the latch. When the value
of clock is 1, takes on the value of 1 if the value of set is 1 and
the value of 0 if the value of reset is 1.
output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, set_, reset, clock, output, output_not):
wire_1 = Wire()
Expand All @@ -67,16 +56,14 @@ def __init__(self, set_, reset, clock, output, output_not):


class GatedDLatch:
"""
This class simulates a gated D latch, which has two inputs, including a
clock, and two outputs:
________
data ----| |---- output
clock ----|________|---- output_not
If clock is 0, output and output_not hold their current values, regardless
of the data input. If clock is 1, output takes on the value of data and
output_not takes on the opposite value.
"""Construct a new gated D latch.
Args:
data: An object of type Wire. The data input to the latch.
clock: An object of type Wire. The clock input to the latch.
output: An object of type Wire. The output of the latch. Takes on the
value of data if the value of clock is 1.
output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, data, clock, output, output_not):
wire_1 = Wire()
Expand All @@ -86,17 +73,14 @@ def __init__(self, data, clock, output, output_not):


class DFlipFlop:
"""
This class simulates a D flip-flop, which has two inputs, including a
clock, and two outputs:
________
data ----| |---- output
clock ----|________|---- output_not
On the positive edge of clock (i.e. on the clock transition from a 0 value
to a 1 value), output takes on the value of data and output_not takes on
the opposite value. Otherwise, output and output_not hold their current
values.
"""Construct a new positive edge-triggered D flip-flop.
Args:
data: An object of type Wire. The data input to the flip-flop.
clock: An object of type Wire. The clock input to the flip-flop.
output: An object of type Wire. The output of the flip-flop. Takes on
the value of data on the positive edges of clock.
output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, data, clock, output, output_not):
q_1 = Wire()
Expand All @@ -109,24 +93,19 @@ def __init__(self, data, clock, output, output_not):


class DFlipFlopPresetClear:
"""
This class simulates a D flip-flop, with additional inputs for presetting
and clearing the flip_flop. It has four inputs, including a clock, and two
outputs:
________
data ----| |---- output
preset_n ----| |---- output_not
clear_n ----| |
clock ----|________|
On the positive edge of clock (i.e. on the clock transition from a 0 value
to a 1 value), output takes on the value of data and output_not takes on
the opposite value. Otherwise, output and output_not hold their current
values.
Inputs preset_n and clear_n are, respectively, an active low
asynchronous preset (setting output to 1 and output_not to 0) and an active
low asynchronous clear (setting output to 0 and output_not to 1).
"""Construct a new positive edge-triggered D flip-flop with preset/clear
capabilities.
Args:
data: An object of type Wire. The data input to the flip-flop.
preset_n: An object of type Wire. Presets output to 1 and output_not to
0 if its value is 0.
clear_n: An object of type Wire. Clears output to 0 and output_not to 1
if its value is 0.
clock: An object of type Wire. The clock input to the flip-flop.
output: An object of type Wire. The output of the flip-flop. Takes on
the value of data on the positive edges of clock.
output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, data, preset_n, clear_n, clock, output, output_not):
not_clock = Wire()
Expand All @@ -151,17 +130,15 @@ def __init__(self, data, preset_n, clear_n, clock, output, output_not):


class TFlipFlop:
"""
This class simulates a T flip-flop, which has two inputs, including a
clock, and two outputs:
________
toggle ----| |---- output
clock ----|________|---- output_not
On the positive edge of clock (i.e. on the clock transition from a 0 value
to a 1 value), if toggle has the value 1, both output and output_not toggle
their current values. If toggle has the value 0, both output and output_not
are unchanged.
"""Construct a new positive edge-triggered T flip-flop.
Args:
toggle: An object of type Wire. The toggle input to the flip-flop.
clock: An object of type Wire. The clock input to the flip-flop.
output: An object of type Wire. The output of the flip-flop. Toggles
its value on the positive edges of clock if the value of toggle is
1.
output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, toggle, clock, output, output_not):
mux_output = Wire()
Expand All @@ -173,24 +150,20 @@ def __init__(self, toggle, clock, output, output_not):


class TFlipFlopPresetClear:
"""
This class simulates a T flip-flop, with additional inputs for presetting
and clearing the flip_flop. It has four inputs, including a clock, and two
outputs:
________
toggle ----| |---- output
preset_n ----| |---- output_not
clear_n ----| |
clock ----|________|
On the positive edge of clock (i.e. on the clock transition from a 0 value
to a 1 value), if toggle has the value 1, both output and output_not toggle
their current values. If toggle has the value 0, both output and output_not
are unchanged.
Inputs preset_n and clear_n are, respectively, an active low
asynchronous preset (setting output to 1 and output_not to 0) and an active
low asynchronous clear (setting output to 0 and output_not to 1).
"""Construct a new positive edge-triggered T flip-flop with preset/clear
capabilities.
Args:
toggle: An object of type Wire. The toggle input to the flip-flop.
preset_n: An object of type Wire. Presets output to 1 and output_not to
0 if its value is 0.
clear_n: An object of type Wire. Clears output to 0 and output_not to 1
if its value is 0.
clock: An object of type Wire. The clock input to the flip-flop.
output: An object of type Wire. The output of the flip-flop. Toggles
its value on the positive edges of clock if the value of toggle is
1.
output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, toggle, preset_n, clear_n, clock, output, output_not):
mux_output = Wire()
Expand All @@ -209,20 +182,17 @@ def __init__(self, toggle, preset_n, clear_n, clock, output, output_not):


class JKFlipFlop:
"""
This class simulates a JK flip-flop, which has three inputs, including a
clock, and two outputs:
________
J ----| |---- output
K ----| |---- output_not
clock ----|________|
On the positive edge of clock (i.e. on the clock transition from a 0 value
to a 1 value), if J is 1 and K is 0, output and output_not are 1 and 0,
respectively. If J is 0 and K is 1, output and output_not are 0 and 1,
respectively. If J and K are both 0, both output and output_not hold their
current values. If J and K are both 1, both output and output_not toggle
their current values.
"""Construct a new positive edge-triggered JK flip-flop.
Args:
J: An object of type Wire. The J input to the flip-flop.
K: An object of type Wire. The K input to the flip-flop.
clock: An object of type Wire. The clock input to the flip-flop.
output: An object of type Wire. The output of the flip-flop. On the
positive edges of clock, takes on the value of 1 if the value of J
is 1, takes on the value of 0 if the value of K is 1, and toggles
its value if both J and K have value 1.
output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, j, k, clock, output, output_not):
and_1 = Wire()
Expand All @@ -238,27 +208,22 @@ def __init__(self, j, k, clock, output, output_not):


class JKFlipFlopPresetClear:
"""
This class simulates a JK flip-flop, with additional inputs for presetting
and clearing the flip_flop. It has five inputs, including a clock, and two
outputs:
________
J ----| |---- output
K ----| |---- output_not
preset_n ----| |
clear_n ----| |
clock ----|________|
On the positive edge of clock (i.e. on the clock transition from a 0 value
to a 1 value), if J is 1 and K is 0, output and output_not are 1 and 0,
respectively. If J is 0 and K is 1, output and output_not are 0 and 1,
respectively. If J and K are both 0, both output and output_not hold their
current values. If J and K are both 1, both output and output_not toggle
their current values.
Inputs preset_n and clear_n are, respectively, an active low
asynchronous preset (setting output to 1 and output_not to 0) and an active
low asynchronous clear (setting output to 0 and output_not to 1).
"""Construct a new positive edge-triggered JK flip-flop with preset/clear
capabilities.
Args:
J: An object of type Wire. The J input to the flip-flop.
K: An object of type Wire. The K input to the flip-flop.
preset_n: An object of type Wire. Presets output to 1 and output_not to
0 if its value is 0.
clear_n: An object of type Wire. Clears output to 0 and output_not to 1
if its value is 0.
clock: An object of type Wire. The clock input to the flip-flop.
output: An object of type Wire. The output of the flip-flop. On the
positive edges of clock, takes on the value of 1 if the value of J
is 1, takes on the value of 0 if the value of K is 1, and toggles
its value if both J and K have value 1.
output_not: An object of type Wire. The complemented form of output.
"""
def __init__(self, j, k, preset_n, clear_n, clock, output, output_not):
and_1 = Wire()
Expand Down
Loading

0 comments on commit 705c6e7

Please sign in to comment.