cranelift-interpreter: Fix panic when bitcasting SIMD values

Fixes bytecodealliance#5915
jan-justin · May 31, 2023 · 34b609f · 34b609f
1 parent c044790
commit 34b609f
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Showing 2 changed files with 41 additions and 5 deletions.
diff --git a/cranelift/filetests/filetests/runtests/simd-bitcast.clif b/cranelift/filetests/filetests/runtests/simd-bitcast.clif
@@ -35,3 +35,36 @@ block0(v0: f64x2):
 }
 ; run: %bitcast_fi64x2([0x0.0 -NaN:0x7ffffffffffff]) == [0 18446744073709551615]
 ; run: %bitcast_fi64x2([-NaN:0x7ffffffffffff 0x0.000000000007fp-1022]) == [-1 127]
+
+function %bitcast_more_lanes_little(i64x2) -> i32x4 {
+block0(v0: i64x2):
+    v1 = bitcast.i32x4 little v0
+    return v1
+}
+; run: %bitcast_more_lanes_little(0x00000000000000000000000000000000) == 0x00000000000000000000000000000000
+; run: %bitcast_more_lanes_little(0x00000000000000ff00000000000000ff) == 0x00000000000000ff00000000000000ff
+
+function %bitcast_fewer_lanes_little(i16x8) -> i64x2 {
+block0(v0: i16x8):
+    v1 = bitcast.i64x2 little v0
+    return v1
+}
+; run: %bitcast_fewer_lanes_little(0x00000000000000000000000000000000) == 0x00000000000000000000000000000000
+; run: %bitcast_fewer_lanes_little(0x00ff0000000000000000000000000000) == 0x00ff0000000000000000000000000000
+
+function %bitcast_more_lanes_big(i64x2) -> i32x4 {
+block0(v0: i64x2):
+    v1 = bitcast.i32x4 big v0
+    return v1
+}
+; run: %bitcast_more_lanes_big(0x00000000000000ff00000000000000ff) == 0x00000000000000ff00000000000000ff
+; run: %bitcast_more_lanes_big(0x00000000000000000000000000000000) == 0x00000000000000000000000000000000
+
+function %bitcast_fewer_lanes_big(i16x8) -> i64x2 {
+block0(v0: i16x8):
+    v1 = bitcast.i64x2 big v0
+    return v1
+}
+; run: %bitcast_fewer_lanes_big(0x00000000000000000000000000000000) == 0x00000000000000000000000000000000
+; run: %bitcast_fewer_lanes_big(0x00ff00ff000000ff00000000000000ff) == 0x00ff00ff000000ff00000000000000ff
+; run: %bitcast_fewer_lanes_big(0x00ff00ff000000000000000000000000) == 0x00ff00ff000000000000000000000000
diff --git a/cranelift/interpreter/src/step.rs b/cranelift/interpreter/src/step.rs
@@ -904,11 +904,14 @@ where
         Opcode::IsInvalid => unimplemented!("IsInvalid"),
         Opcode::Bitcast | Opcode::ScalarToVector => {
             let input_ty = inst_context.type_of(inst_context.args()[0]).unwrap();
-            let arg0 = extractlanes(&arg(0), input_ty)?;
-            let lanes = &arg0
-                .into_iter()
-                .map(|x| DataValue::convert(x, ValueConversionKind::Exact(ctrl_ty.lane_type())))
-                .collect::<ValueResult<SimdVec<DataValue>>>()?;
+            let lanes = &if input_ty.is_vector() {
+                extractlanes(&arg(0), ctrl_ty)?
+            } else {
+                extractlanes(&arg(0), input_ty)?
+                    .into_iter()
+                    .map(|x| DataValue::convert(x, ValueConversionKind::Exact(ctrl_ty.lane_type())))
+                    .collect::<ValueResult<SimdVec<DataValue>>>()?
+            };
             assign(match inst.opcode() {
                 Opcode::Bitcast => vectorizelanes(lanes, ctrl_ty)?,
                 Opcode::ScalarToVector => vectorizelanes_all(lanes, ctrl_ty)?,