Project Description : 
  This project is aimed to implement Viola-Jones Algorithm in FPGA for cars' detection. It described
  in VHDL and was written in ISE 14.7 environment.It had been successfully simulated using ISim Simulator 
  and implemented on Digilent Nexys2 FPGA Development Board with Spartan 3E-500 FG-320 FPGA Core.
  
  The project was started in November 2019 and had been done in February 2020 by Jason D. Setiawan 
  under the guidance of Brawijaya University Electrical Engineering Department's lecturers,
  R. Arief Setyawan, M.T and Adharul Muttaqin, M.T.
  
Contents of Repository:
  1. Readme.txt
      Contains Project Description and Repository's contents.
  2. Full Project folder
      Contains all the files generated by ISE during designing, simulation, and implementation process.
  3. Training Folder
      Contains all the files for ROM (in .coe) including test image (in .coe) and cascade classifier training 
      from OpenCV (in .xml).
  4. VHDL Folder
      Contains all entities which had be build (in .vhd). Core generated entities are not included.