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Fix tristate bug512, broken with tristate commit.
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#!/usr/bin/perl | ||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } | ||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
# | ||
# Copyright 2003 by Wilson Snyder. This program is free software; you can | ||
# redistribute it and/or modify it under the terms of either the GNU | ||
# Lesser General Public License Version 3 or the Perl Artistic License | ||
# Version 2.0. | ||
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compile ( | ||
); | ||
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# No exeecution | ||
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ok(1); | ||
1; |
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// DESCRIPTION: Verilator: Verilog Test module | ||
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module t (/*AUTOARG*/ | ||
// Inputs | ||
clk | ||
); | ||
input clk; | ||
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tri pad_io_h; | ||
tri pad_io_l; | ||
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sub sub (.*); | ||
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endmodule | ||
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module sub (/*AUTOARG*/ | ||
// Inouts | ||
pad_io_h, pad_io_l | ||
); | ||
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parameter USE = 1'b1; | ||
parameter DIFFERENTIAL = 1'b1; | ||
parameter BIDIR = 1'b1; | ||
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inout pad_io_h; | ||
inout pad_io_l; | ||
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wire [31:0] dqs_out_dtap_delay; | ||
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generate | ||
if (USE) begin: output_strobe | ||
wire aligned_os_oe; | ||
wire aligned_strobe; | ||
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if (BIDIR) begin | ||
reg sig_h_r = 1'b0; | ||
reg sig_l_r = 1'b0; | ||
always @* begin | ||
sig_h_r = ~aligned_os_oe ? aligned_strobe : 1'bz; | ||
if (DIFFERENTIAL) | ||
sig_l_r = ~aligned_os_oe ? ~aligned_strobe : 1'bz; | ||
end | ||
assign pad_io_h = sig_h_r; | ||
if (DIFFERENTIAL) | ||
assign pad_io_l = sig_l_r; | ||
end | ||
end | ||
endgenerate | ||
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endmodule | ||
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