Mersenne-twister-hardware

A flexible hardware module written in SystemVerilog which implements the Mersene twister (using a 32-bit word length). A simulation and a test bench written in SystemC, which use Verilator were created in order to verify the correctness and to measure performance of the hardware module.

Installation

Clone the repository:

git clone git@github.com:Jeudine/Mersenne-twister-hardware.git

If you will be using the simulation and the test bench, download SystemC and Verilator.

Once downloaded, run make in the root of the repository to build the project.

Usage

The top module is defined with the following parameters and ports:

module MTwister #(parameter
    N = 624, // degree of recurrence
    M = 397, // middle word
    R = 31, // separation point of one word
    A = 32'h9908B0DF, // coefficients of the rational normal form twist matrix
    U = 11, // shift size used in the tempering process
    D = 32'hFFFFFFFF, // XOR mask used in the tempering process
    S = 7, // shift size used in tempering process
    B = 32'h9D2C5680, // XOR mask used in the tempering process
    T = 15, // shift size used in tempering process
    C = 32'hEFC60000, // XOR mask used in the tempering process
    L = 18, // shift size used in tempering process
    F = 1812433253 // initialization parameter
) (
    input clk, rst, trig,
    input [31:0] seed,
    output [31:0] r_num,
    output ready,
    output last
);

The reset (rst) is synchronous and positive-logic. Once rst becomes low, the module is initialized with the value of the seed signal.

During the Initialization and the Generation, the signal ready is low. This signal is high when numbers are ready to be extracted.

When ready is high, each time trig will be high during a rising edge of clk, a new random number will be extracted the next rising edge of clk on the r_num output (the value holds until the next number extraction).

The signal last is high if and only if there’s only one number left to extract. It indicates the last extraction before the next Generation.

The default parameters correspond to the standard MT19937.

All the Systemverilog code used to implement the MTwister module can be found in src/.

Simulation and test bench

Run ./simulation.x <value of the seed> to execute the simulation. During the execution some information are directly printed on the standard output.

A functional module of the Mersenne Twister written in C++ (MTwister_func) is used to verify the correctness of the SystemVerilog module. The default parameters used for this module are the same as those used for MTwister, but feel free to play with tb_src/Parameters.h in order to test other parameters.

During the simulation two .vcd trace files will be generated:

• simu_trace.vcd contains all the input/output signals of the MTwister module and also those of the MTwister_func sc_module.

• debug_trace.vcd contains all the internal signals of the MTwister module. This trace file makes debug easier.

Performance

Duration

• Initialization: N periods

• Generation: 2N + 1 periods

• Minimum Extraction duration for N values: N periods

Extraction

This module allows Burst Transfer, i.e., you can hold the signal trig high in order to have a new random number at each clk cycle.