Add aligned attribute to avoid issues with gcc5+ when accessing regis…

…ters
jgarff · Mar 25, 2016 · 0e5a3db · 0e5a3db
1 parent af8a710
commit 0e5a3db
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Showing 4 changed files with 5 additions and 5 deletions.
diff --git a/clk.h b/clk.h
@@ -51,7 +51,7 @@ typedef struct {
 #define CM_PWM_DIV_PASSWD                        (0x5a << 24)
 #define CM_PWM_DIV_DIVI(val)                     ((val & 0xfff) << 12)
 #define CM_PWM_DIV_DIVF(val)                     ((val & 0xfff) << 0)
-} __attribute__ ((packed)) cm_pwm_t;
+} __attribute__((packed, aligned(4))) cm_pwm_t;
 
 
 #define CM_PWM_OFFSET                            (0x001010a0)

diff --git a/dma.h b/dma.h
@@ -46,7 +46,7 @@ typedef struct
     uint32_t stride;
     uint32_t nextconbk;
     uint32_t resvd_0x18[2];
-} __attribute__((packed)) dma_cb_t;
+} __attribute__((packed, aligned(4))) dma_cb_t;
 
 /*
  * DMA register set
@@ -95,7 +95,7 @@ typedef struct
 #define RPI_DMA_STRIDE_S_STRIDE(val)             ((val & 0xffff) << 0)
     uint32_t nextconbk;
     uint32_t debug;
-} __attribute__((packed)) dma_t;
+} __attribute__((packed, aligned(4))) dma_t;
 
 
 #define DMA0_OFFSET                              (0x00007000)

diff --git a/gpio.h b/gpio.h
@@ -59,7 +59,7 @@ typedef struct
     uint32_t pudclk[2];                          // GPIO Pin Pull up/down Enable Clock
     uint32_t resvd_0xa0[4];
     uint32_t test;
-} __attribute__((packed)) gpio_t;
+} __attribute__((packed, aligned(4))) gpio_t;
 
 
 #define GPIO_OFFSET                              (0x00200000)

diff --git a/pwm.h b/pwm.h
@@ -96,7 +96,7 @@ typedef struct
     uint32_t resvd_0x1c;
     uint32_t rng2;
     uint32_t dat2;
-} __attribute__((packed)) pwm_t;
+} __attribute__((packed, aligned(4))) pwm_t;
 
 
 #define PWM_OFFSET                               (0x0020c000)