Merge 12b453b into b9c1da8

src/main/scala/memory/base-memory-components.scala

@@ -2,7 +2,9 @@
 
 package dinocpu.memory
 
+import dinocpu.memory.MemoryOperation._
 import chisel3._
+import chisel3.util.{Decoupled, Valid}
 import chisel3.util.experimental.loadMemoryFromFile
 
 /**
@@ -22,8 +24,17 @@ abstract class BaseDualPortedMemory(size: Int, memfile: String) extends Module {
     val imem = new MemPortBusIO
     val dmem = new MemPortBusIO
   })
-  io.imem <> 0.U.asTypeOf (new MemPortBusIO)
-  io.dmem <> 0.U.asTypeOf (new MemPortBusIO)
+
+  // Intentional DontCares:
+  // The connections between the ports and the backing memory, along with the
+  // ports internally assigning values to the, means that these DontCares
+  // should be completely 'overwritten' when the CPU is elaborated
+  io.imem.request <> DontCare
+  io.dmem.request <> DontCare
+  // Zero out response ports to 0, so that the pipeline does not receive any
+  // 'DontCare' values from the memory ports
+  io.imem.response <> 0.U.asTypeOf(Valid (new Response))
+  io.dmem.response <> 0.U.asTypeOf(Valid (new Response))
 
   val memory = Mem(math.ceil(size.toDouble/4).toInt, UInt(32.W))
   loadMemoryFromFile(memory, memfile)
@@ -39,7 +50,11 @@ abstract class BaseIMemPort extends Module {
   })
 
   io.pipeline <> 0.U.asTypeOf (new IMemPortIO)
-  io.bus      <> 0.U.asTypeOf (new MemPortBusIO)
+  // Intentional DontCare:
+  // The connections between the ports and the backing memory, along with the
+  // ports internally assigning values to the, means that these DontCares
+  // should be completely 'overwritten' when the CPU is elaborated
+  io.bus      <> DontCare
 }
 
 /**
@@ -52,7 +67,11 @@ abstract class BaseDMemPort extends Module {
   })
 
   io.pipeline <> 0.U.asTypeOf (new DMemPortIO)
-  io.bus      <> 0.U.asTypeOf (new MemPortBusIO)
+  // Intentional DontCare:
+  // The connections between the ports and the backing memory, along with the
+  // ports internally assigning values to the, means that these DontCares
+  // should be completely 'overwritten' when the CPU is elaborated
+  io.bus      <> DontCare
 
   io.pipeline.good := io.bus.response.valid
 }

src/main/scala/memory/memory-noncombin-ports.scala

@@ -34,7 +34,7 @@ class DNonCombinMemPort extends BaseDMemPort {
 
   // A register to hold intermediate data (e.g., write data, mask mode) while the request
   // is outstanding to memory.
-  val outstandingReq = RegInit(0.U.asTypeOf(Valid(new OutstandingReq)))
+  val outstandingReq = RegInit (0.U.asTypeOf (Valid (new OutstandingReq)))
 
   // Used to set the valid bit of the outstanding request
   val sending = Wire(Bool())

src/main/scala/memory/memory.scala

@@ -24,7 +24,7 @@ class DualPortedCombinMemory(size: Int, memfile: String) extends BaseDualPortedM
 
   when (io.imem.request.valid) {
     // Put the Request into the instruction pipe and signal that instruction memory is busy
-    val request = io.imem.request.asTypeOf(new Request)
+    val request = io.imem.request.bits
 
     // We should only be expecting a read from instruction memory
     assert(request.operation === Read)
@@ -50,7 +50,7 @@ class DualPortedCombinMemory(size: Int, memfile: String) extends BaseDualPortedM
   val memWriteData = io.dmem.request.bits.writedata
 
   when (io.dmem.request.valid) {
-    val request = io.dmem.request.asTypeOf (new Request)
+    val request = io.dmem.request.bits
 
     // Check that non-combin write isn't being used
     assert (request.operation =/= Write)

src/main/scala/pipelined/stage-register.scala

@@ -21,16 +21,17 @@ class StageRegIO[+T <: Data](gen: T) extends Bundle {
 
   /** The outputted data from the internal register */
   val data = Output(gen)
+
+  override def cloneType: this.type = StageRegIO (gen).asInstanceOf[this.type]
 }
 
 /**
   * Factory to wrap a data bundle in a stage register IO interface.
   */
 object StageRegIO {
-  def apply[T <: Data](gen: T): StageRegIO[T] = new StageRegIO(gen)
+  def apply[T <: Data](gen: T): StageRegIO[T] = new StageRegIO (gen)
 }
 
-
 /** A specialized register module that supports freezing, flushing,
   * and writing to its contents when valid.
   */