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Merge 85215c0 into 7de3ad5
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@powerjg
powerjg committed Jan 3, 2020
2 parents 7de3ad5 + 85215c0 commit 846a55f
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Showing 7 changed files with 171 additions and 79 deletions.
3 changes: 0 additions & 3 deletions src/main/scala/configuration.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -34,9 +34,6 @@ class CPUConfig
/** The backing memory type */
var memType = "combinational"

/** For debugging output */
var debug = false

/**
* Returns the CPU that we will be elaborating
*
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15 changes: 0 additions & 15 deletions src/main/scala/pipelined/cpu-bp.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -125,8 +125,6 @@ class PipelinedCPUBP(implicit val conf: CPUConfig) extends BaseCPU {
// registers, we create an anonymous Bundle
val mem_wb_ctrl = Module(new StageReg(new MEMWBControl))

if (conf.debug) { printf("Cycle=%d ", cycleCount) }

// For tracking branch predictor stats
val bpCorrect = RegInit(0.U(32.W))
val bpIncorrect = RegInit(0.U(32.W))
Expand Down Expand Up @@ -158,8 +156,6 @@ class PipelinedCPUBP(implicit val conf: CPUConfig) extends BaseCPU {
(hazard.io.pcwrite === 2.U) -> pc,
(hazard.io.pcwrite === 3.U) -> id_next_pc))

if (conf.debug) { printf(p"PC: $pc\n") }

// Send the PC to the instruction memory port to get the instruction
io.imem.address := pc

Expand All @@ -181,8 +177,6 @@ class PipelinedCPUBP(implicit val conf: CPUConfig) extends BaseCPU {
// Flush IF/ID when required
if_id.io.flush := hazard.io.ifid_flush

if (conf.debug) { printf(p"IF/ID: $if_id\n") }

/////////////////////////////////////////////////////////////////////////////
// ID STAGE
/////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -260,9 +254,6 @@ class PipelinedCPUBP(implicit val conf: CPUConfig) extends BaseCPU {
// Flush the id_ex control block with 0 when bubbling
id_ex_ctrl.io.flush := hazard.io.idex_bubble

if (conf.debug) { printf("DASM(%x)\n", if_id.io.data.instruction) }
if (conf.debug) { printf(p"ID/EX: $id_ex\n") }

/////////////////////////////////////////////////////////////////////////////
// EX STAGE
/////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -380,8 +371,6 @@ class PipelinedCPUBP(implicit val conf: CPUConfig) extends BaseCPU {
// Flush EXMEM's control signals if there is a bubble
ex_mem_ctrl.io.flush := hazard.io.exmem_bubble

if (conf.debug) { printf(p"EX/MEM: $ex_mem\n") }

/////////////////////////////////////////////////////////////////////////////
// MEM STAGE
/////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -426,8 +415,6 @@ class PipelinedCPUBP(implicit val conf: CPUConfig) extends BaseCPU {
// Stall pipeline if neither instruction nor data.mem_ctrl.mory are ready
val memStall = ~(io.imem.good && io.dmem.good)

if (conf.debug) { printf(p"MEM/WB: $mem_wb\n") }

/////////////////////////////////////////////////////////////////////////////
// WB STAGE
/////////////////////////////////////////////////////////////////////////////
Expand All @@ -446,6 +433,4 @@ class PipelinedCPUBP(implicit val conf: CPUConfig) extends BaseCPU {
// Set the input signals for the forwarding unit
forwarding.io.memwbrd := mem_wb.io.data.writereg
forwarding.io.memwbrw := mem_wb_ctrl.io.data.wb_ctrl.regwrite

if (conf.debug) { printf("---------------------------------------------\n") }
}
43 changes: 30 additions & 13 deletions src/main/scala/pipelined/cpu.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -123,8 +123,6 @@ class PipelinedCPU(implicit val conf: CPUConfig) extends BaseCPU {
// registers, we create an anonymous Bundle
val mem_wb_ctrl = Module(new StageReg(new MEMWBControl))

if (conf.debug) { printf("Cycle=%d ", cycleCount) }

// Forward declaration of wires that connect different stages

// From memory back to fetch. Since we don't decide whether to take a branch or not until the memory stage.
Expand All @@ -140,7 +138,6 @@ class PipelinedCPU(implicit val conf: CPUConfig) extends BaseCPU {

// Note: This comes from the memory stage!
// Only update the pc if the pcwrite flag is enabled
if (conf.debug) { printf(p"PC: $pc\n") }
pc := MuxCase(0.U, Array(
(hazard.io.pcwrite === 0.U) -> pcPlusFour.io.result,
(hazard.io.pcwrite === 1.U) -> next_pc,
Expand Down Expand Up @@ -168,8 +165,6 @@ class PipelinedCPU(implicit val conf: CPUConfig) extends BaseCPU {

if_id.io.flush := hazard.io.ifid_flush

if (conf.debug) { printf(p"IF/ID: $if_id\n") }

/////////////////////////////////////////////////////////////////////////////
// ID STAGE
/////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -231,9 +226,6 @@ class PipelinedCPU(implicit val conf: CPUConfig) extends BaseCPU {
// bubble
id_ex_ctrl.io.flush := hazard.io.idex_bubble

if (conf.debug) { printf("DASM(%x)\n", if_id.io.data.instruction) }
if (conf.debug) { printf(p"ID/EX: $id_ex\n") }

/////////////////////////////////////////////////////////////////////////////
// EX STAGE
/////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -324,8 +316,6 @@ class PipelinedCPU(implicit val conf: CPUConfig) extends BaseCPU {
// Flush the EXMEM control signals if the hazard s a bubble
ex_mem_ctrl.io.flush := hazard.io.exmem_bubble

if (conf.debug) { printf(p"EX/MEM: $ex_mem\n") }

/////////////////////////////////////////////////////////////////////////////
// MEM STAGE
/////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -367,8 +357,6 @@ class PipelinedCPU(implicit val conf: CPUConfig) extends BaseCPU {
mem_wb_ctrl.io.flush := false.B
mem_wb_ctrl.io.in.wb_ctrl := ex_mem_ctrl.io.data.wb_ctrl

if (conf.debug) { printf(p"MEM/WB: $mem_wb\n") }

/////////////////////////////////////////////////////////////////////////////
// WB STAGE
/////////////////////////////////////////////////////////////////////////////
Expand All @@ -387,6 +375,35 @@ class PipelinedCPU(implicit val conf: CPUConfig) extends BaseCPU {
// Set the input signals for the forwarding unit
forwarding.io.memwbrd := mem_wb.io.data.writereg
forwarding.io.memwbrw := mem_wb_ctrl.io.data.wb_ctrl.regwrite
}

if (conf.debug) { printf("---------------------------------------------\n") }
/*
* Object to make it easier to print information about the CPU
*/
object PipelinedCPUInfo {
def getModules(): List[String] = {
List(
"control",
"branchCtrl",
"registers",
"aluControl",
"alu",
"immGen",
"pcPlusFour",
"branchAdd",
"forwarding",
"hazard",
)
}
def getPipelineRegs(): List[String] = {
List(
"if_id",
"id_ex",
"id_ex_ctrl",
"ex_mem",
"ex_mem_ctrl",
"mem_wb",
"mem_wb_ctrl"
)
}
}
2 changes: 1 addition & 1 deletion src/main/scala/replrunner.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ object replrunner {
}

//setup test
val driver = new CPUTesterDriver(cpuType, predictor, test.binary, test.extraName, true)
val driver = new CPUTesterDriver(cpuType, predictor, test.binary, test.extraName)
driver.initRegs(test.initRegs)
driver.initMemory(test.initMem)

Expand Down
42 changes: 19 additions & 23 deletions src/main/scala/single-cycle/cpu.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -119,28 +119,24 @@ class SingleCycleCPU(implicit val conf: CPUConfig) extends BaseCPU {
next_pc := pcPlusFour.io.result
}

// Debug / pipeline viewer
val structures = List(
(control, "control"),
(registers, "registers"),
(csr, "csr"),
(aluControl, "aluControl"),
(alu, "alu"),
(immGen, "immGen"),
(branchCtrl, "branchCtrl"),
(pcPlusFour, "pcPlusFour"),
(branchAdd, "branchAdd")
)

if (conf.debug) {
printf("DASM(%x)\n", instruction)
printf(p"CYCLE=$cycleCount\n")
printf(p"pc: $pc\n")
for (structure <- structures) {
printf(p"${structure._2}: ${structure._1.io}\n")
}
printf("\n")
}

pc := next_pc
}

/*
* Object to make it easier to print information about the CPU
*/
object SingleCycleCPUInfo {
def getModules(): List[String] = {
List(
"control",
"registers",
"csr",
"aluControl",
"alu",
"immGen",
"branchCtrl",
"pcPlusFour",
"branchAdd"
)
}
}
67 changes: 59 additions & 8 deletions src/main/scala/singlestep.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -9,13 +9,31 @@ object singlestep {
val helptext = "usage: singlestep <test name> <CPU type>"

val commands = """Help for the single stepper:
| Note: Registers print the value *stored* in that register. The wires print
| the *current* value on the wire for that cycle.
|
| Printing registers
| ------------------
| print reg <num> : print the value in register
| print regs : print values in all registers
| print pc : print the address in the pc
| print inst [addr]: print the disassembly for the instruction at addr.
| If no addr provided then use the current pc.
|
| Printing module I/O (wires)
| ---------------------------
| dump all : Show all modules and the values of their I/O
| dump list : List the valid modules to dump
| dump [module] : Show values of the I/O on a specific module
|
| Controlling the simulator
| -------------------------
| step [num] : move forward this many cycles, default 1
|
| Other commands
| --------------
| ? : print this help
| print reg <num> : print the value in register
| print regs : print values in all registers
| print pc : print the address in the pc
| print inst : print the disassembly for the current instruction
| q : quit
| step [num] : move forward this many cycles, default 1
|""".stripMargin

def doPrint(tokens: Array[String], driver: CPUTesterDriver): Boolean = {
Expand All @@ -41,13 +59,41 @@ object singlestep {
true
}
case "inst" => {
driver.printInst()
true
if (tokens.length == 2) {
driver.printInst()
true
} else if (tokens.length == 3) {
try {
driver.printInst(tokens(2).toInt)
true
} catch {
case e: NumberFormatException => false
}
} else {
false
}
}
case _ => false
}
}

def doDump(tokens: Array[String], driver: CPUTesterDriver): Boolean = {
tokens(1) match {
case "all" => {
driver.dumpAllModules()
true
}
case "list" => {
driver.listModules()
true
}
case _ => {
driver.dumpModule(tokens(1))
true
}
}
}

def doStep(tokens: Array[String], driver: CPUTesterDriver): Boolean = {
val cycles = try {
if (tokens.length == 2) tokens(1).toInt else 1
Expand Down Expand Up @@ -84,7 +130,7 @@ object singlestep {
println(commands)
var done = false
while (!done) {
val tokens = scala.io.StdIn.readLine("Single stepper > ").split(" ")
val tokens = scala.io.StdIn.readLine("Single stepper> ").split(" ")
if (tokens.length > 0) {
tokens(0) match {
case "?" => println(commands)
Expand All @@ -95,6 +141,11 @@ object singlestep {
if (!doPrint(tokens, driver)) println(commands)
}
}
case "dump" => {
if (tokens.length > 1) {
if (!doDump(tokens, driver)) println(commands)
}
}
case _ => println(commands)
}
}
Expand Down

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