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Feature/vunit #32

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wants to merge 5 commits into from
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Feature/vunit #32

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lukipedio
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Maybe you've already set up something for VUnit.
This is my experimenting stuff.
Add a run.py to the root folder with add_source_files for all current folders (see possible use of glob library).
The simulation is currently broken by incorrect record fields usage in the ethernet hierarchy.
This pull request is just indicative of a possible integration.
I have ran a test with:
python run.py --compile
by setting up gdhl as compiler/simultator

Add .gitignore rule to ignore vunit_out temporary folder
@lukipedio lukipedio mentioned this pull request Aug 15, 2021
@lukipedio lukipedio marked this pull request as draft August 18, 2021 13:57
@lukipedio
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I am getting these errors from compilation:
image
Could you please help me get rid of them?

@johonkanen
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johonkanen commented Aug 18, 2021

The ddr io simulation sources are remnant of the initial design of rgmii receiver which had different header paclage structure for clocking. Since correctly designed ddrio returns a octet per clock cycle, those arch_simulatio_rx_ddrio sources should be deleted as obsolete. It is better to simulate the rx receiver control object directly.

@lukipedio lukipedio closed this Aug 20, 2021
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2 participants