Master/slave mode

[gyurco]

From the MAME sources:
https://github.com/mamedev/mame/blob/master/src/devices/sound/msm5205.cpp#L31

It's actually used on the Irem M62 sound board, where two of these chips are connected. Of course now it's possible to use the same lines to S1 and S2, and the chips will probably be in sync.

[jotego]

Wow! An undocumented feature. I'll look into it. Thank you.

[gyurco]

Further debugging the Irem M62 sound board shows that it's actually causing problems when the VCLK (IRQ) is outputting if both S lines are high. So at least the irq should be disabled in this case (I can send a patch, if you prefer, not much work).

[gyurco]

Yet another issue discovered: as IRQ is not a real VCLK output, it's not suitable for using it for a CPU interrupt line (cpu68 NMI in the Irem case), because it's only valid for one clock cycle. A normal VCLK with 50% duty cycle is OK.
(Sorry for torturing your code)

[gyurco]

My modifications are here (maybe a bit hacky):
https://github.com/gyurco/Mist_FPGA/blob/loderunner/Arcade_MiST/IremM62%20Hardware/rtl/jt5205/jt5205_timing.v#L44
This satisfies the Irem sound board requirements about the vclk output (and should be similar to the original chip). vclk_i is not implemented, it can be worked around by supplying the same S inputs to both chips.