Fixes CPS1/CPS15/SF. See #324

jotego · Sep 8, 2023 · 1e5a491 · 1e5a491
1 parent 6de30ff
commit 1e5a491
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Showing 4 changed files with 4 additions and 4 deletions.
diff --git a/cores/cps1/hdl/jtcps1_main.v b/cores/cps1/hdl/jtcps1_main.v
@@ -180,7 +180,7 @@ always @(posedge clk, posedge rst) begin
         main2qs_addr <= 23'd0;
         `endif
     end else begin
-        if( !ASn && BGACKn ) begin // PAL PRG1 12H
+        if( !ASn && BGACKn && (RnW || {UDSn,LDSn}!=3) ) begin // PAL PRG1 12H
             rom_addr    <= A[21:1];
             rom_cs      <= A[23:22] == 2'b00;
             // dbus_cs     <= ~|A[23:18]; // all must be zero

diff --git a/cores/karnov/hdl/jtkarnov_main.v b/cores/karnov/hdl/jtkarnov_main.v
@@ -132,7 +132,7 @@ always @* begin
     dmarq     = 0;
     pos_cs    = 0;
     vint_ctl  = 0;
-    if( !ASn ) begin
+    if( !ASn && (RnW || dsn!=3)) begin
         rom_cs    = A[21:17]<=2; // 00000~5FFFF
         pre_ram_cs= A[21:17]==3; // 60000~6FFFF
         objram_cs = A[21:17]==4; // 80000

diff --git a/cores/sf/hdl/jtsf_main.v b/cores/sf/hdl/jtsf_main.v
@@ -187,7 +187,7 @@ always @(*) begin
     mcu_DMAONn = 1;
     regs_cs    = 0;
 
-    if( (!CPUbus && mcu_acc_s) ||  (!ASn && BGACKn) ) begin
+    if( (!CPUbus && mcu_acc_s) ||  (!ASn && BGACKn && (RnW || {UDSn,LDSn}!=3)) ) begin
         case(Aeff[23:20])
             4'h0: rom_cs  = 1;  // reading from the ROM may fail from the MCU, but it shouldn't matter
             4'h8: char_cs = 1;

diff --git a/modules/jtframe/hdl/cpu/jtframe_68kdtack.v b/modules/jtframe/hdl/cpu/jtframe_68kdtack.v
@@ -128,7 +128,7 @@ end
 always @(posedge clk) begin
     cencnt  <= cencnt_nx[CW] ? {CW{1'b1}} : cencnt_nx[CW-1:0];
     if( rst ) cencnt <= 0;
-    if( (over && !halt) || rst ) begin
+    if( over || rst || halt ) begin
         cpu_cen  <= risefall;
         cpu_cenb <= ~risefall;
         risefall <= ~risefall;