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#382 WIP
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@jotego
jotego committed Jan 17, 2024
1 parent d58940b commit 6d62d0f
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Showing 6 changed files with 53 additions and 26 deletions.
2 changes: 1 addition & 1 deletion modules/jtframe/bin/jtbin2mr
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Expand Up @@ -11,7 +11,7 @@ a MiSTer device in the network.
Usage:
jtbin2mr.sh [-l|--local]
jtbin2mr [-l|--local]
-l, --local Uses JTROOT/release instead of JTBIN (default)
-m, --mr MiSTer host name or IP address
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19 changes: 12 additions & 7 deletions modules/jtframe/bin/jtrelease.sh
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@@ -1,11 +1,6 @@
#!/bin/bash
# Make a release to JTBIN from GitHub builds

if [ ! -d "$JTBIN/.git" ]; then
echo "\$JTBIN must point to a git repository"
exit 0
fi

set -e

HASH="$1"
Expand Down Expand Up @@ -39,8 +34,18 @@ if [ -d /media/$USER/POCKET ]; then
jtbin2sd &
fi

cd $JTBIN
cp -r $DST/release/* .
if ping -c 1 -q $MRHOST > /dev/null; then
jtbin2mr
fi

if [[ -n "$JTBIN" && -d "$JTBIN" ]]; then
cd $JTBIN
cp -r $DST/release/* .
else
echo "Skipping JTBIN as \$JTBIN is not defined"
exit 0
fi


wait
rm -rf $DST
25 changes: 16 additions & 9 deletions modules/jtframe/ver/sdram_bank64/prog_test/test.v
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Expand Up @@ -74,8 +74,8 @@ always @(posedge clk, posedge rst) begin
end
end

reg downloading;
reg [24:0] ioctl_addr;
reg ioctl_rom;
reg [25:0] ioctl_addr;
wire [ 7:0] ioctl_dout;
wire ioctl_wr;
wire [21:0] prog_addr;
Expand All @@ -101,14 +101,14 @@ always @(posedge clk, posedge rst) begin

ioctl_addr <= 0;
timer <= 31;
downloading <= 0;
ioctl_rom <= 0;
end else begin
if( sdram_ack )
lfsr <= { lfsr[0], lfsr[28], lfsr[27]^lfsr[0], lfsr[26:1] };
timer <= timer-1;
if( timer==1 ) begin
ioctl_addr <= ioctl_addr+1;
downloading <= 1;
ioctl_rom <= 1;
if( &ioctl_addr ) begin
$display("All 32MB written");
$finish;
Expand All @@ -129,25 +129,32 @@ jtframe_sdram64 #(
.rst ( rst ),
.clk ( clk ),
.rfsh ( hblank ),
.init ( ),
// Bank 0: allows R/W
.ba0_addr ( ),
.ba1_addr ( ),
.ba2_addr ( ),
.ba3_addr ( ),
.rd ( 4'd0 ),
.wr ( 4'd0 ),
.din ( ),
.din_m ( ), // write mask
.ba0_din ( ),
.ba0_dsn ( ), // write mask
.ba1_din ( ),
.ba1_dsn ( ), // write mask
.ba2_din ( ),
.ba2_dsn ( ), // write mask
.ba3_din ( ),
.ba3_dsn ( ), // write mask
.rdy ( ),
.dok ( ),
.ack ( ),

.prog_en ( downloading ),
.prog_en ( ioctl_rom ),
.prog_addr ( prog_addr ),
.prog_rd ( prog_rd ),
.prog_wr ( prog_we ),
.prog_din ( prog_data ),
.prog_din_m ( prog_mask ),
.prog_dsn ( prog_mask ),
.prog_ba ( prog_ba ),
.prog_dst ( ),
.prog_dok ( ),
Expand All @@ -174,7 +181,7 @@ jtframe_dwnld #(
.BA3_START( 25'h3_000 )
) u_dwnld(
.clk ( clk ),
.downloading( downloading ),
.ioctl_rom ( ioctl_rom ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout ),
.ioctl_wr ( ioctl_wr ),
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2 changes: 1 addition & 1 deletion modules/jtframe/ver/sdram_bank64/romrq_dst/sim.sh
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Expand Up @@ -3,7 +3,7 @@
make || exit $?
HDL=../../../hdl

iverilog $HDL/sdram/jtframe_{sdram64*,rom_1slot,romrq}.v test.v \
iverilog $HDL/sdram/jtframe_{sdram64*,rom_1slot,rom_2slots,romrq,romrq_bcache,ramslot_ctrl}.v test.v \
$HDL/ver/mt48lc16m16a2.v -s test -o xsim \
-DSIMULATION -DSDRAM_SHIFT=3 -DJTFRAME_SDRAM_BANKS \
-DDUMP -Ptest.SIMLEN=3 && xsim -lxt
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21 changes: 15 additions & 6 deletions modules/jtframe/ver/sdram_bank64/romrq_dst/test.v
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Expand Up @@ -49,7 +49,10 @@ end
initial begin
rst=1;
#100 rst=0;
#(SIMLEN*1_000_000) $finish;
#(SIMLEN*1_000_000) begin
$display("PASS");
$finish;
end
end

// horizontal line counter
Expand Down Expand Up @@ -109,7 +112,7 @@ jtframe_rom_1slot #(.SLOT0_DW( 8),.SLOT0_AW(12)) u_bank0(
.slot0_ok ( slot0_ok ),
// SDRAM controller interface
.sdram_ack ( ba_ack[0] ),
.sdram_req ( ba_rd[0] ),
.sdram_rd ( ba_rd[0] ),
.sdram_addr ( ba0_addr ),
.data_rdy ( ba_rdy[0] ),
.data_dst ( ba_dst[0] ),
Expand All @@ -126,7 +129,7 @@ jtframe_rom_1slot #(.SLOT0_DW(16),.SLOT0_AW(12)) u_bank1(
.slot0_ok ( slot1_ok ),
// SDRAM controller interface
.sdram_ack ( ba_ack[1] ),
.sdram_req ( ba_rd[1] ),
.sdram_rd ( ba_rd[1] ),
.sdram_addr ( ba1_addr ),
.data_rdy ( ba_rdy[1] ),
.data_dst ( ba_dst[1] ),
Expand All @@ -143,7 +146,7 @@ jtframe_rom_1slot #(.SLOT0_DW(32),.SLOT0_AW(12)) u_bank2(
.slot0_ok ( slot2_ok ),
// SDRAM controller interface
.sdram_ack ( ba_ack[2] ),
.sdram_req ( ba_rd[2] ),
.sdram_rd ( ba_rd[2] ),
.sdram_addr ( ba2_addr ),
.data_rdy ( ba_rdy[2] ),
.data_dst ( ba_dst[2] ),
Expand Down Expand Up @@ -186,8 +189,14 @@ jtframe_sdram64 #(
.ba3_addr ( ba3_addr ),
.rd ( ba_rd ),
.wr ( ba_wr ),
.din ( ba0_din ),
.din_m ( ba0_din_m ), // write mask
.ba0_din ( ba0_din ),
.ba0_dsn ( ba0_din_m ), // write mask
.ba1_din ( ),
.ba1_dsn ( ), // write mask
.ba2_din ( ),
.ba2_dsn ( ), // write mask
.ba3_din ( ),
.ba3_dsn ( ), // write mask
.rdy ( ba_rdy ),
.dok ( ba_dok ),
.dst ( ba_dst ),
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10 changes: 8 additions & 2 deletions modules/jtframe/ver/sdram_bank64/rw_test/test.v
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Expand Up @@ -216,8 +216,14 @@ jtframe_sdram64 #(
.ba3_addr ( ba3_addr ),
.rd ( rd ),
.wr ( wr ),
.din ( ba0_din ),
.din_m ( ba0_din_m ), // write mask
.ba0_din ( ba0_din ),
.ba0_dsn ( ba0_din_m ), // write mask
.ba1_din ( ),
.ba1_dsn ( ), // write mask
.ba2_din ( ),
.ba2_dsn ( ), // write mask
.ba3_din ( ),
.ba3_dsn ( ), // write mask
.rdy ( rdy ),
.dok ( dok ),
.ack ( ack ),
Expand Down

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