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cen signals defined in mem.yaml for kicker mikie pinpon roadf roc sba…
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…skt track
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@jotego
jotego committed May 4, 2023
1 parent 1ae267d commit 8fd2fc0
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Showing 17 changed files with 87 additions and 137 deletions.
1 change: 0 additions & 1 deletion cores/kicker/cfg/common.yaml
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Expand Up @@ -5,7 +5,6 @@ game:
- jtkicker_scroll.v
- jtkicker_obj.v
- jtkicker_objdraw.v
- jtkicker_clocks.v
jtframe:
- get:
- jtframe_ff.v
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10 changes: 10 additions & 0 deletions cores/kicker/cfg/mem.yaml
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Expand Up @@ -2,6 +2,16 @@ params:
- { name: SCR_OFFSET, value: "`SCR_START >> 1" }
- { name: OBJ_OFFSET, value: "`OBJ_START >> 1" }
- { name: PCM_OFFSET, value: "`PCM_START >> 1" }

clocks:
clk24:
- mul: 1
div: 4
outputs:
- cpu4
- ti1
- ti2

download:
post_addr: true
noswab: true
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48 changes: 0 additions & 48 deletions cores/kicker/hdl/jtkicker_clocks.v
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This file was deleted.

13 changes: 1 addition & 12 deletions cores/kicker/hdl/jtkicker_game.v
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Expand Up @@ -30,7 +30,7 @@ wire [ 3:0] dipsw_c;
wire V16;

wire [ 2:0] pal_sel;
wire cpu_cen, cpu4_cen, ti1_cen, ti2_cen;
wire cpu_cen;
wire cpu_rnw, cpu_irqn, cpu_nmin;
wire vscr_cs, vram_cs, obj1_cs, obj2_cs, flip;
wire [ 7:0] vscr_dout, vram_dout, obj_dout, cpu_dout;
Expand All @@ -55,17 +55,6 @@ always @(*) begin
end
end

jtkicker_clocks u_clocks(
.status ( status ),
// 24 MHz domain
.clk24 ( clk24 ),
.cpu4_cen ( cpu4_cen ),
.snd_cen ( ),
.psg_cen ( ),
.ti1_cen ( ti1_cen ),
.ti2_cen ( ti2_cen )
);

`ifndef NOMAIN
`MAIN_MODULE u_main(
.rst ( rst24 ),
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10 changes: 10 additions & 0 deletions cores/mikie/cfg/mem.yaml
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Expand Up @@ -2,6 +2,16 @@ params:
- { name: SCR_OFFSET, value: "`SCR_START >> 1" }
- { name: OBJ_OFFSET, value: "`OBJ_START >> 1" }
- { name: SND_OFFSET, value: "`SND_START >> 1" }

clocks:
clk24:
- mul: 1
div: 4
outputs:
- cpu4
- ti1
- ti2

download:
pre_addr: true
post_data: true
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13 changes: 1 addition & 12 deletions cores/mikie/hdl/jtmikie_game.v
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Expand Up @@ -32,7 +32,7 @@ wire [ 1:0] dipsw_c;
wire V16;

wire [ 2:0] pal_sel;
wire cpu_cen, cpu4_cen, ti1_cen, ti2_cen;
wire cpu_cen;
wire cpu_rnw, cpu_irqn, cpu_nmin;
wire vram_cs, objram_cs, flip;
wire [ 7:0] vscr_dout, vram_dout, obj_dout, cpu_dout;
Expand Down Expand Up @@ -68,17 +68,6 @@ always @(*) begin
end
end

jtkicker_clocks u_clocks(
.status ( status ),
// 24 MHz domain
.clk24 ( clk24 ),
.cpu4_cen ( cpu4_cen ),
.snd_cen ( ),
.psg_cen ( ),
.ti1_cen ( ti1_cen ),
.ti2_cen ( ti2_cen )
);

`ifndef NOMAIN
jtmikie_main u_main(
.rst ( rst24 ),
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10 changes: 10 additions & 0 deletions cores/pinpon/cfg/mem.yaml
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@@ -1,6 +1,16 @@
params:
- { name: SCR_OFFSET, value: "`SCR_START >> 1" }
- { name: OBJ_OFFSET, value: "`OBJ_START >> 1" }

clocks:
clk24:
- mul: 1
div: 4
outputs:
- cpu4
- ti1
- ti2

download:
pre_addr: true
sdram:
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13 changes: 1 addition & 12 deletions cores/pinpon/hdl/jtpinpon_game.v
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Expand Up @@ -30,7 +30,7 @@ wire [ 7:0] dipsw_a, dipsw_b;
wire [ 2:0] dipsw_c; // The bit 3 is not connected on the board
wire V16;

wire cpu_cen, cpu4_cen, ti1_cen, ti2_cen;
wire cpu_cen;
wire cpu_rnw, cpu_irqn, cpu_nmin;
wire vram_cs, oram_cs, flip;
wire [ 7:0] vram_dout, obj_dout, cpu_dout;
Expand All @@ -57,17 +57,6 @@ always @(*) begin
end
end

jtkicker_clocks u_clocks(
.status ( status ),
// 24 MHz domain
.clk24 ( clk24 ),
.cpu4_cen ( cpu4_cen ),
.snd_cen ( ),
.psg_cen ( ),
.ti1_cen ( ti1_cen ),
.ti2_cen ( ti2_cen )
);

`ifndef NOMAIN
assign snd[4:0]=0;

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13 changes: 13 additions & 0 deletions cores/roadf/cfg/mem.yaml
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Expand Up @@ -3,6 +3,19 @@ params:
- { name: OBJ_OFFSET, value: "`OBJ_START >> 1" }
- { name: PCM_OFFSET, value: "`PCM_START >> 1" }
- { name: SND_OFFSET, value: "`SND_START >> 1" }
clocks:
clk24:
- mul: 1
div: 4
outputs:
- cpu4
- ti1
- ti2
- freq: 3579545
outputs:
- snd
- psg

download:
post_addr: true
post_data: true
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14 changes: 1 addition & 13 deletions cores/roadf/hdl/jtroadf_game.v
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Expand Up @@ -31,11 +31,10 @@ wire [ 7:0] dipsw_a, dipsw_b;
wire [ 2:0] dipsw_c;

wire obj_frame;
wire cpu_cen, cpu4_cen;
wire cpu_cen;
wire cpu_rnw, cpu_irqn, cpu_nmin;
wire vram_cs, objram_cs, flip;
wire [ 7:0] vram_dout, obj_dout, cpu_dout;
wire snd_cen, psg_cen;

wire m2s_irq, m2s_data;
wire main_pause;
Expand Down Expand Up @@ -72,17 +71,6 @@ always @(posedge clk) begin
is_hyper <= &prog_data;
end

jtkicker_clocks u_clocks(
.status ( status ),
// 24 MHz domain
.clk24 ( clk24 ),
.cpu4_cen ( cpu4_cen ),
.snd_cen ( snd_cen ),
.psg_cen ( psg_cen ),
.ti1_cen ( ),
.ti2_cen ( )
);

`ifndef NOMAIN
jtroadf_main u_main(
.rst ( rst24 ),
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8 changes: 8 additions & 0 deletions cores/roc/cfg/mem.yaml
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Expand Up @@ -2,6 +2,14 @@ params:
- { name: SCR_OFFSET, value: "`SCR_START >> 1" }
- { name: OBJ_OFFSET, value: "`OBJ_START >> 1" }
- { name: SND_OFFSET, value: "`SND_START >> 1" }

clocks:
clk24:
- mul: 1
div: 4
outputs:
- cpu4

download:
post_addr: true
sdram:
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13 changes: 1 addition & 12 deletions cores/roc/hdl/jtroc_game.v
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Expand Up @@ -31,7 +31,7 @@ wire [10:0] cpu_addr;
wire [ 7:0] st_main, st_snd;
reg [ 7:0] view_mux;

wire cpu_cen, cpu4_cen, ti1_cen, ti2_cen;
wire cpu_cen;
wire cpu_rnw, cpu_irqn, cpu_nmin;
wire vram_cs, objram_cs, flip;
wire [ 7:0] vram_dout, obj_dout, cpu_dout;
Expand Down Expand Up @@ -68,17 +68,6 @@ always @(*) begin
end
end

jtkicker_clocks u_clocks(
.status ( status ),
// 24 MHz domain
.clk24 ( clk24 ),
.cpu4_cen ( cpu4_cen ),
.snd_cen ( ),
.psg_cen ( ),
.ti1_cen ( ),
.ti2_cen ( )
);

`ifndef NOMAIN
jtroc_main u_main(
.rst ( rst24 ),
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14 changes: 14 additions & 0 deletions cores/sbaskt/cfg/mem.yaml
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Expand Up @@ -3,6 +3,20 @@ params:
- { name: OBJ_OFFSET, value: "`OBJ_START >> 1" }
- { name: PCM_OFFSET, value: "`PCM_START >> 1" }
- { name: SND_OFFSET, value: "`SND_START >> 1" }

clocks:
clk24:
- mul: 1
div: 4
outputs:
- cpu4
- ti1
- ti2
- freq: 3579545
outputs:
- snd
- psg

download:
post_data: true
sdram:
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14 changes: 1 addition & 13 deletions cores/sbaskt/hdl/jtsbaskt_game.v
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Expand Up @@ -28,13 +28,12 @@ wire V16;

wire [ 3:0] pal_sel;
wire obj_frame;
wire cpu_cen, cpu4_cen;
wire cpu_cen;
wire cpu_rnw, cpu_irqn, cpu_nmin;
wire vscr_cs, vram_cs, objram_cs, flip;
wire [ 7:0] vscr_dout, vram_dout, obj_dout, cpu_dout,
debug_snd;
wire vsync60;
wire snd_cen, psg_cen;

wire m2s_irq, m2s_data;

Expand All @@ -51,17 +50,6 @@ always @(*) begin
end
end

jtkicker_clocks u_clocks(
.status ( status ),
// 24 MHz domain
.clk24 ( clk24 ),
.cpu4_cen ( cpu4_cen ),
.snd_cen ( snd_cen ),
.psg_cen ( psg_cen ),
.ti1_cen ( ),
.ti2_cen ( )
);

`ifndef NOMAIN
jtsbaskt_main u_main(
.rst ( rst24 ),
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14 changes: 14 additions & 0 deletions cores/track/cfg/mem.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,20 @@ params:
- { name: OBJ_OFFSET, value: "`OBJ_START >> 1" }
- { name: SND_OFFSET, value: "`SND_START >> 1" }
- { name: PCM_OFFSET, value: "`PCM_START >> 1" }

clocks:
clk24:
- mul: 1
div: 4
outputs:
- cpu4
- ti1
- ti2
- freq: 3579545
outputs:
- snd
- psg

download:
post_addr: true
post_data: true
Expand Down
14 changes: 1 addition & 13 deletions cores/track/hdl/jttrack_game.v
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Expand Up @@ -29,11 +29,10 @@ localparam [24:0] PROM_START = `JTFRAME_PROM_START;

wire [ 7:0] dipsw_a, dipsw_b;

wire cpu_cen, cpu4_cen;
wire cpu_cen;
wire cpu_rnw, cpu_irqn, cpu_nmin;
wire vram_cs, objram_cs, flip;
wire [ 7:0] vram_dout, obj_dout, cpu_dout;
wire snd_cen, psg_cen;

wire m2s_irq, m2s_data;
wire main_pause;
Expand All @@ -58,17 +57,6 @@ always @(*) begin
end
end

jtkicker_clocks u_clocks(
.status ( status ),
// 24 MHz domain
.clk24 ( clk24 ),
.cpu4_cen ( cpu4_cen ),
.snd_cen ( snd_cen ),
.psg_cen ( psg_cen ),
.ti1_cen ( ),
.ti2_cen ( )
);

`ifndef NOMAIN
jttrack_main u_main(
.rst ( rst24 ),
Expand Down
2 changes: 1 addition & 1 deletion modules/jtframe
Submodule jtframe updated from 18cd39 to 225493

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