No SDRAM bank gets stalled even in very busy situations

jotego · Jan 19, 2024 · cb09824 · cb09824
1 parent e613a27
commit cb09824
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Showing 2 changed files with 9 additions and 4 deletions.
diff --git a/modules/jtframe/hdl/sdram/jtframe_sdram64.v b/modules/jtframe/hdl/sdram/jtframe_sdram64.v
@@ -354,6 +354,7 @@ jtframe_sdram64_bank #(
 ) u_bank0(
     .rst        ( other_rst  ),
     .clk        ( clk        ),
+    .help       ( help       ),
 
     // requests
     .addr       ( ba0_addr_l ),
@@ -401,6 +402,7 @@ jtframe_sdram64_bank #(
 ) u_bank1(
     .rst        ( other_rst  ),
     .clk        ( clk        ),
+    .help       ( help       ),
 
     // requests
     .addr       ( ba1_addr_l ),
@@ -447,6 +449,7 @@ jtframe_sdram64_bank #(
 ) u_bank2(
     .rst        ( other_rst  ),
     .clk        ( clk        ),
+    .help       ( help       ),
 
     // requests
     .addr       ( ba2_addr_l ),
@@ -493,6 +496,7 @@ jtframe_sdram64_bank #(
 ) u_bank3(
     .rst        ( other_rst  ),
     .clk        ( clk        ),
+    .help       ( help       ),
 
     // requests
     .addr       ( ba3_addr_l ),
@@ -532,7 +536,7 @@ jtframe_sdram64_bank #(
 always @(*) begin
     rfsh_bg = &idle && (noreq | help) && rfsh_br;
     prog_bg = pre_br & !rfshing;
-    if( rfshing | help ) begin
+    if( rfshing ) begin
         bg=0;
     end else begin
         if( BAPRIO ) begin

diff --git a/modules/jtframe/hdl/sdram/jtframe_sdram64_bank.v b/modules/jtframe/hdl/sdram/jtframe_sdram64_bank.v
@@ -32,6 +32,7 @@ module jtframe_sdram64_bank #(
 )(
     input               rst,
     input               clk,
+    input               help,
 
     // requests
     input      [AW-1:0] addr,
@@ -153,7 +154,7 @@ end
 always @(*) begin
     rot_st  = { st[STW-2:0], st[STW-1] };
     next_st = st;
-    if( st[IDLE] ) begin
+    if( st[IDLE] & ~help) begin
         if(do_prech) next_st = rot_st;
         if(do_act  ) next_st = ONE<<ACT;
         if(do_read ) next_st = ONE<<READ;
@@ -191,7 +192,7 @@ generate
                 br <= 0;
             end else begin
                 br <= 0;
-                if( (st[IDLE] || next_st[IDLE] || next_st[PRE_ACT] || next_st[PRE_RD]) && rd_wr ) begin
+                if( ( ((st[IDLE] || next_st[IDLE])&&!help) || next_st[PRE_ACT] || next_st[PRE_RD]) && rd_wr ) begin
                     br <= 1;
                     if( next_st[PRE_RD] & (all_dbusy | (all_dbusy64&wr)) ) br <= 0; // Do not try to request
                 end
@@ -200,7 +201,7 @@ generate
     end else begin
         always @(*) begin
             br = 0;
-            if( (st[IDLE] || st[PRE_ACT] || st[PRE_RD]) && rd_wr ) begin
+            if( ( (st[IDLE]&&!help) || st[PRE_ACT] || st[PRE_RD]) && rd_wr ) begin
                 br = 1;
                 if( st[PRE_RD] & (all_dbusy | (all_dbusy64&wr)) ) br = 0; // Do not try to request
             end