Fixed Shinobi bonus stage that broke after the fix for #279

jotego · Jul 6, 2023 · cf58e37 · cf58e37
1 parent f6995e3
commit cf58e37
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Showing 3 changed files with 13 additions and 12 deletions.
diff --git a/cores/s16/hdl/jts16_scr.v b/cores/s16/hdl/jts16_scr.v
@@ -22,6 +22,7 @@ module jts16_scr(
     input              pxl2_cen,  // pixel clock enable (2x)
     input              pxl_cen,   // pixel clock enable
 
+    input              LVBL,
     input              LHBL,
     input              start,
     input              alt_en,
@@ -174,11 +175,11 @@ always @(posedge clk, posedge rst) begin
         scr_good  <= { scr_good[0] & scr_ok, scr_ok };
         if( scr_good==2'b01 ) pxl_data <= scr_data[23:0];
 
-        if( start && !start_l ) begin
+        if( (start && !start_l) ) begin
             vscan <= vrf;
             done  <= 0;
             busy  <= 0;
-            bad   <= !done;
+            bad   <= LVBL && !done; // SDRAM activity halted during most of VB
             hscan <= HSCAN0;
         end
 

diff --git a/cores/s16/hdl/jts16_tilemap.v b/cores/s16/hdl/jts16_tilemap.v
@@ -262,6 +262,7 @@ jts16_scr #(.PXL_DLY(SCR1_DLY),.HB_END(HB_END),.MODEL(MODEL)) u_scr1(
     .pxl2_cen  ( pxl2_cen       ),
     .pxl_cen   ( pxl_cen        ),
     .LHBL      ( preLHBL        ),
+    .LVBL      ( preLVBL        ),
 
     .start     ( scr_start      ),
     .alt_en    ( alt_en         ),
@@ -301,6 +302,7 @@ jts16_scr #(.PXL_DLY(SCR2_DLY[8:0]),.MODEL(MODEL)) u_scr2(
     .pxl2_cen  ( pxl2_cen       ),
     .pxl_cen   ( pxl_cen        ),
     .LHBL      ( preLHBL        ),
+    .LVBL      ( preLVBL        ),
 
     .start     ( scr_start      ),
     .alt_en    ( alt_en         ),

diff --git a/modules/jtframe/hdl/cpu/jtframe_68kdtack.v b/modules/jtframe/hdl/cpu/jtframe_68kdtack.v
@@ -78,7 +78,7 @@ module jtframe_68kdtack
 localparam CW=W+WD;
 
 reg [CW-1:0] cencnt=0;
-reg  [2:0]   wait1;
+reg  [1:0]   waitsh;
 wire         halt;
 wire [W-1:0] num2 = { num, 1'b0 }; // num x 2
 wire over = cencnt>den-num2;
@@ -94,26 +94,24 @@ reg  risefall=0;
     wire rstl=0;
 `endif
 
-assign halt = !rstl && RECOVERY==1 && !ASn && wait1==0 && (bus_cs && bus_busy && !bus_legit);
+assign halt = !rstl && RECOVERY==1 && !ASn && waitsh==0 && (bus_cs && bus_busy && !bus_legit);
 
 
 always @(posedge clk) begin : dtack_gen
     if( rst ) begin
         DTACKn <= 1;
-        wait1  <= 3'b111;
+        waitsh <= 0;
     end else begin
         if( ASn | &DSn ) begin // DSn is needed for read-modify-write cycles
                // performed on the SDRAM. Just checking the DSn rising edge
                // is not enough on Rastan
             DTACKn <= 1;
-            wait1  <= 3'b111;
+            waitsh <= {wait3,wait2 | ASn} ; // ASn will be high for read-modify-write cycles
+            // those cycles need special attention as they easily get broken
+            // See https://github.com/ijor/fx68k/issues/7
         end else if( !ASn ) begin
-            if( cpu_cen ) case( {wait3,wait2} )
-                0: wait1 <= 0;
-                1: wait1 <= {2'b0, wait1[1] };
-                2,3: wait1 <= {1'b0, wait1[2:1] };
-            endcase
-            if( wait1==0 /*&& (!bus_cs || (bus_cs && !bus_busy))*/ ) begin
+            if( cpu_cen ) waitsh <= waitsh>>1;
+            if( waitsh==0 ) begin
                 DTACKn <= 0;
             end
         end