moved signal back to internal as it is not needed as a port

jotego · Nov 1, 2023 · 2a44a7f · 2a44a7f
1 parent 24b477c
commit 2a44a7f
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Showing 2 changed files with 1 addition and 4 deletions.
diff --git a/hdl/jtopl_reg.v b/hdl/jtopl_reg.v
@@ -81,7 +81,6 @@ parameter OPL_TYPE=1;
 localparam CH=9;
 
 wire [2:0] subslot;
-wire [1:0] next_group;
 
 wire       update_op_I  = !write && sel_group == group && sel_sub == subslot;
 reg        update_op_II, update_op_III, update_op_IV;
@@ -94,7 +93,6 @@ jtopl_slot_cnt u_slot_cnt(
     // Pipeline order
     .zero       ( zero      ),
     .group      ( group     ),
-    .next_group (next_group ),
     .op         ( op        ),   // 0 for modulator operators
     .subslot    ( subslot   ),
     .slot       ( slot      )    // hot one encoding of active slot

diff --git a/hdl/jtopl_slot_cnt.v b/hdl/jtopl_slot_cnt.v
@@ -27,7 +27,6 @@ module jtopl_slot_cnt(
     // Pipeline order
     output            zero,
     output reg [ 1:0] group,
-    output     [ 1:0] next_group,
     output reg        op,           // 0 for modulator operators    
     output reg [ 2:0] subslot,
     output reg [17:0] slot         // hot one encoding of active slot
@@ -36,7 +35,7 @@ module jtopl_slot_cnt(
 // Each group contains three channels
 // and each subslot contains six operators
 wire [2:0] next_sub   = subslot==3'd5 ? 3'd0 : (subslot+3'd1);
-assign next_group = subslot==3'd5 ? (group==2'b10 ? 2'b00 : group+2'b1) : group;
+wire [1:0] next_group = subslot==3'd5 ? (group==2'b10 ? 2'b00 : group+2'b1) : group;
 
 `ifdef SIMULATION
 // These signals need to operate during rst