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target-arm: add secure/normal world banks of SCTLR register
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Johannes Winter committed Jun 11, 2013
1 parent 5e3800e commit d0598d6
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Showing 4 changed files with 18 additions and 13 deletions.
2 changes: 1 addition & 1 deletion hw/arm/pxa2xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -277,7 +277,7 @@ static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
case 3:
s->cpu->env.uncached_cpsr =
ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
s->cpu->env.cp15.c1_sys = 0;
s->cpu->env.cp15.c1_sys.secure = 0;
s->cpu->env.cp15.c1_coproc = 0;
s->cpu->env.cp15.c2_base0 = 0;
s->cpu->env.cp15.c3 = 0;
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2 changes: 1 addition & 1 deletion target-arm/cpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -121,7 +121,7 @@ typedef struct CPUARMState {
struct {
uint32_t c0_cpuid;
uint32_t c0_cssel; /* Cache size selection. */
uint32_t c1_sys; /* System control register. */
arm_banked32_t c1_sys; /* System control register. */
uint32_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint32_t c1_scr; /* secure config register. */
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24 changes: 14 additions & 10 deletions target-arm/helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1051,7 +1051,8 @@ static const ARMCPRegInfo trustzone_cp_reginfo[] = {

static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
env->cp15.c1_sys = value;
/* We currently treat all (unimplemented) bits as banked bits. */
CPREG_FIELD32(env, ri) = value;
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(env, 1);
Expand Down Expand Up @@ -1282,7 +1283,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo sctlr = {
.name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
.writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
.type = ARM_CP_BANKED
};
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
/* Normally we would always end the TB on an SCTLR write, but Linux
Expand Down Expand Up @@ -1998,8 +2000,8 @@ void arm_cpu_do_interrupt(CPUState *cs)
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
return; /* Never happens. Keep compiler happy. */
}
int to_secure = (new_mode == ARM_CPU_MODE_SMC) || !(env->cp15.c1_scr & SCR_NS);
if (arm_feature(env, ARM_FEATURE_TRUSTZONE)) {
int to_secure = (new_mode == ARM_CPU_MODE_SMC) || !(env->cp15.c1_scr & SCR_NS);
if (!to_secure) {
/* Honor SCR.AW/SCR.FW in normal world */
if (!(env->cp15.c1_scr & SCR_FW)) {
Expand All @@ -2013,15 +2015,15 @@ void arm_cpu_do_interrupt(CPUState *cs)
(env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SMC) {
addr += env->cp15.c12_mvbar;
} else {
if (env->cp15.c1_sys & (1 << 13)) {
if (CP15_BANK32(env, c1_sys, to_secure) & (1 << 13)) {
addr += 0xffff0000;
} else {
addr += CP15_BANK32(env, c12_vbar, to_secure);
}
}
} else {
/* High vectors. */
if (env->cp15.c1_sys & (1 << 13)) {
if (CP15_BANK32(env, c1_sys, to_secure) & (1 << 13)) {
addr += 0xffff0000;
}
}
Expand All @@ -2035,7 +2037,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
* and we should just guard the thumb mode on V4 */
if (arm_feature(env, ARM_FEATURE_V4T)) {
env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
env->thumb = (CP15_BANK32(env, c1_sys, to_secure) & (1 << 30)) != 0;
}
env->regs[14] = env->regs[15] + offset;
env->regs[15] = addr;
Expand All @@ -2048,6 +2050,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
int access_type, int is_user)
{
int core_is_secure = arm_current_secure(env);
int prot_ro;

if (domain_prot == 3) {
Expand All @@ -2063,7 +2066,7 @@ static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
case 0:
if (access_type == 1)
return 0;
switch ((env->cp15.c1_sys >> 8) & 3) {
switch ((CP15_BANK32(env, c1_sys, core_is_secure) >> 8) & 3) {
case 1:
return is_user ? 0 : PAGE_READ;
case 2:
Expand Down Expand Up @@ -2217,6 +2220,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
int domain = 0;
int domain_prot;
hwaddr phys_addr;
int core_is_secure = arm_current_secure(env);

/* Pagetable walk. */
/* Lookup l1 descriptor. */
Expand Down Expand Up @@ -2295,7 +2299,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
goto do_fault;

/* The simplified model uses AP[0] as an access control bit. */
if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
if ((CP15_BANK32(env, c1_sys, core_is_secure) & (1 << 29)) && (ap & 1) == 0) {
/* Access flag fault. */
code = (code == 15) ? 6 : 3;
goto do_fault;
Expand Down Expand Up @@ -2589,7 +2593,7 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address,
if (address < 0x02000000)
address += CP15_BANK32(env, c13_fcse, is_secure);

if ((env->cp15.c1_sys & 1) == 0) {
if ((CP15_BANK32(env, c1_sys, is_secure) & 1) == 0) {
/* MMU/MPU disabled. */
*phys_ptr = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
Expand All @@ -2602,7 +2606,7 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address,
} else if (extended_addresses_enabled(env)) {
return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
prot, page_size);
} else if (env->cp15.c1_sys & (1 << 23)) {
} else if (CP15_BANK32(env, c1_sys, is_secure) & (1 << 23)) {
return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
prot, page_size);
} else {
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3 changes: 2 additions & 1 deletion target-arm/machine.c
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Original file line number Diff line number Diff line change
Expand Up @@ -136,6 +136,7 @@ static const VMStateDescription vmstate_normal_world = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.cp15.c1_sys.normal, ARMCPU),
VMSTATE_UINT32(env.cp15.c12_vbar.normal, ARMCPU),
VMSTATE_UINT32(env.cp15.c13_context.normal, ARMCPU),
VMSTATE_UINT32(env.cp15.c13_fcse.normal, ARMCPU),
Expand Down Expand Up @@ -196,7 +197,7 @@ const VMStateDescription vmstate_arm_cpu = {
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
VMSTATE_UINT32(env.cp15.c0_cpuid, ARMCPU),
VMSTATE_UINT32(env.cp15.c0_cssel, ARMCPU),
VMSTATE_UINT32(env.cp15.c1_sys, ARMCPU),
VMSTATE_UINT32(env.cp15.c1_sys.secure, ARMCPU),
VMSTATE_UINT32(env.cp15.c1_coproc, ARMCPU),
VMSTATE_UINT32(env.cp15.c1_xscaleauxcr, ARMCPU),
VMSTATE_UINT32(env.cp15.c1_scr, ARMCPU),
Expand Down

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