kholoud0

Follow

Kholoud Emam kholoud0

Follow

Electronics and Communication Engineering graduate specializing in Digital IC Design

2 followers · 0 following

in/kholoud-khaled0

Achievements

Achievements

kholoud0/README.md

👋 Hi, i'm Kholoud

🧑‍💻 About me

I am Kholoud Khaled, a fresh Electronics and Communication Engineering graduate from Ain Shams University. I specialize in Digital IC design and am passionate about contributing to innovative projects in this field. My experiences range from ASIC Design & Verification to implementation, and I am always eager to learn and grow in the ever-evolving world of electronics.

🛠️ Technical Skills

Languages: Verilog, VHDL, SystemVerilog, TCL, Python, C, C++
Tools: Synopsys Design Compiler, DFT Compiler, IC Compiler II, PrimeTime, ModelSim, Vivado, MATLAB, Cadence Virtuoso, OpenLane
Key Concepts: ASIC Flow, RTL Coding, Static Timing Analysis (STA), Place and Route (PnR), DFT, Low Power Design, Formal Verification, UVM

Popular repositories Loading

ASIC-implementation-of-CV32E40P-RISC-V-core- ASIC-implementation-of-CV32E40P-RISC-V-core- Public

This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus o…

SystemVerilog 2
Cinema Cinema Public

Forked from nouraan-ahmed/Cinema

JavaScript
stp-task1 stp-task1 Public

JavaScript
Verilog-ASIC-Designs-with-Testbenches Verilog-ASIC-Designs-with-Testbenches Public

Collection of ASIC design projects and testbenches using Verilog. Includes various assignments showcasing design and verification skills.

Verilog
kholoud0 kholoud0 Public