UI interfaced with Date Time module

kiarashplusplus · Dec 10, 2012 · cf2106f · cf2106f
1 parent c75b491
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diff --git a/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.asy b/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.asy
@@ -0,0 +1,30 @@
+Version 4
+SymbolType BLOCK
+
+
+
+RECTANGLE Normal 32 0 256 496
+PIN 0 48  LEFT 36
+PINATTR PinName addra[6:0]
+PINATTR Polarity IN
+LINE Wide 0 48 32 48
+PIN 0 240  LEFT 36
+PINATTR PinName clka
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 0 272  LEFT 36
+PINATTR PinName addrb[6:0]
+PINATTR Polarity IN
+LINE Wide 0 272 32 272
+PIN 0 464  LEFT 36
+PINATTR PinName clkb
+PINATTR Polarity IN
+LINE Normal 0 464 32 464
+PIN 288 48  RIGHT 36
+PINATTR PinName douta[7:0]
+PINATTR Polarity OUT
+LINE Wide 256 48 288 48
+PIN 288 272  RIGHT 36
+PINATTR PinName doutb[7:0]
+PINATTR Polarity OUT
+LINE Wide 256 272 288 272
diff --git a/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.mif b/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.mif
@@ -0,0 +1,100 @@
+00000000
+00000001
+00000010
+00000011
+00000100
+00000101
+00000110
+00000111
+00001000
+00001001
+00010000
+00010001
+00010010
+00010011
+00010100
+00010101
+00010110
+00010111
+00011000
+00011001
+00100000
+00100001
+00100010
+00100011
+00100100
+00100101
+00100110
+00100111
+00101000
+00101001
+00110000
+00110001
+00110010
+00110011
+00110100
+00110101
+00110110
+00110111
+00111000
+00111001
+01000000
+01000001
+01000010
+01000011
+01000100
+01000101
+01000110
+01000111
+01001000
+01001001
+01010000
+01010001
+01010010
+01010011
+01010100
+01010101
+01010110
+01010111
+01011000
+01011001
+01100000
+01100001
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+01110000
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+01110010
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+01110100
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+01111000
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+10000000
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+10010000
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+10010010
+10010011
+10010100
+10010101
+10010110
+10010111
+10011000
+10011001
diff --git a/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.ngc b/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$0004g<,[o}e~g`n;"2*413&;$>"9 > %18456382:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789>;7=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?01234<?>00=2:>5>.1f86s0789hm589"65287457:083>:<924076645:88;=4?7163550739:;9=<??082;42618<:?<>>=002305=1;?8==;>:94:63002=<>>?8<:1427=1>3?=<?99:;350751641:28;>8<52607646:2=1EC^ZT;cg`wg;>3:5=?58:HLSQQ<flmxi0;4?>018<?IR\Y__6iazt`>4>586;221CXZ_UU8gkpre4>0;29>494;7=6?5183;446786:5<0>30:294<6?785;3211?<=?;>9=70532<0?>><=:88;8:CG@WG;8730MIJ]A=33:==FLMXJ0<07;@FGVD:5611JHI\N<2<;?DBCZH6?255NDEPB808?3HNO^L29>99B@ATF4>437LJKR@>;:==FLMXJ0407;@FGVG:7601JHI\M<02=<>GCL[H7=364AEFQF94902KOH_L33?:8EABUJ5>546OKDS@?1;><IMNYN1818:CG@WD;?720MIJ]B=:=<>GCL[H753<4B7:8FPUXAGLD=<5Miocq}ZrhWMohe`oc4:AOOD2<KEAI56M@MLKWP@B03JXNMYKK6:FJE969>2NBM1?16:FJE949>2NBM1=16:FJE929>2NBM1;16:FJE909>2NBM1916:FJF969>2NBN1?16:FJF949>2NBN1=16:FJF929>2NBN1;16:FJF909>2NBN1917:FJTD:76>1OE]L30?48@JG;87<0HBO31?48@JG;:7<0HBO33?48@JG;<7<0HBO35?48@JG;>7<0HBO37?48@JD;87<0HBL31?48@JD;:7<0HBL33?48@JD;<7<0HBL35?48@JD;>7<0HBL37?58@JVF494<7IA_B=2=7>CII:1NBO?4G29DJA><AGC_\R>?8:KMMQVX8820ECG[P^21<>OIA]ZT<>64IOKWTZ6302CEEY^P04:8MKOSXV:=46GAIUR\421<AGC_S=>8;HLJPZ66?2CEEYQ?269JJLRX8:=0ECG[_164?LHN\V:>;6GAIU]322=NF@^T<:94IOKW[5>03@DBXR>67:KMMQY7I>1BBDZP0C58MKOSW9I<7D@FT^2G3>OIA]U;I:5FNHV\4C1<AGC_S<>8;HLJPZ76?2CEEYQ>269JJLRX9:=0ECG[_064?LHN\V;>;6GAIU]222=NF@^T=:94IOKW[4>03@DBXR?67:KMMQY6I>1BBDZP1C58MKOSW8I<7D@FT^3G3>OIA]U:I:5FNHV\5C1<AGC_S?>8;HLJPZ46?2CEEYQ=269JJLRX::=0ECG[_364?LHN\V8>;6GAIU]122=NF@^T>:94IOKW[7>03@DBXR<67:KMMQY5I>1BBDZP2C58MKOSW;I<7D@FT^0G3>OIA]U9I:5FNHV\6C1<AGC_S>>8;HLJPZ56?2CEEYQ<269JJLRX;:=0ECG[_264?LHN\V9>;6GAIU]022=NF@^T?:94IOKW[6>03@DBXR=67:KMMQY4I>1BBDZP3C58MKOSW:I<7D@FT^1G3>OIA]U8I:5FNHV\7C0<AGC_SL84IOKW[G0<DFKOII94LNEJGDJd3DkacXjrrkljf=JageyZh||inl1?K653G;87C??3:L256=I9;90B<=<;O377>H6=:1E=;=4N051?K453G987C=;3:L016=I;?90B>9<;O1;7>H41;1E8>5A4118J1743G>9?6@;329M015<F=?87C:93:L736=I<190B97=;O71?K053G=97C6=;O;4?KCS_FX@=6^;;QCQPd=WAGUIY^GKXc9SMKYE]ZDJAHm4R@OA53YT1VY2:6]@USAF3>UU^HFTM:5\RWCO[G2<[ZXJ86]\RC68P\VBi2_XI_QNLHCPg>STM[U]E^GMLD18RFE>3_CN[RZVPD18S@G43^OIn6Y]IUG\BLTT\j1\^DZJ_LMGAZGd3^XBXHQBOEG\F4b<P@FBBU#WDC"3*4&T\\H+<#?/ARAJMg=_WJEYIRGAFN48\adXAml0TifPPsknR`ttafd:<6Vkm^ObnjtQm{ybcc??;Yfn[Hoig{\n~~g`n99b`atf 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diff --git a/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.sym b/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.sym
@@ -0,0 +1,42 @@
+VERSION 5
+BEGIN SYMBOL Binary_to_Decimal
+SYMBOLTYPE BLOCK
+TIMESTAMP 2012 12 10 8 47 17
+SYMPIN 0 48 Input addra[6:0]
+SYMPIN 0 240 Input clka
+SYMPIN 0 272 Input addrb[6:0]
+SYMPIN 0 464 Input clkb
+SYMPIN 288 48 Output douta[7:0]
+SYMPIN 288 272 Output doutb[7:0]
+RECTANGLE N 32 0 256 496 
+BEGIN DISPLAY 36 48 PIN addra[6:0] ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 0 48 32 48 
+END LINE
+BEGIN DISPLAY 36 240 PIN clka ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 240 32 240 
+BEGIN DISPLAY 36 272 PIN addrb[6:0] ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 0 272 32 272 
+END LINE
+BEGIN DISPLAY 36 464 PIN clkb ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 464 32 464 
+BEGIN DISPLAY 252 48 PIN douta[7:0] ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 256 48 288 48 
+END LINE
+BEGIN DISPLAY 252 272 PIN doutb[7:0] ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 256 272 288 272 
+END LINE
+END SYMBOL
diff --git a/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.v b/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.v
@@ -0,0 +1,141 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file Binary_to_Decimal.v when simulating
+// the core, Binary_to_Decimal. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module Binary_to_Decimal(
+	addra,
+	addrb,
+	clka,
+	clkb,
+	douta,
+	doutb);
+
+
+input [6 : 0] addra;
+input [6 : 0] addrb;
+input clka;
+input clkb;
+output [7 : 0] douta;
+output [7 : 0] doutb;
+
+// synthesis translate_off
+
+      BLKMEMDP_V6_3 #(
+		.c_addra_width(7),
+		.c_addrb_width(7),
+		.c_default_data("0"),
+		.c_depth_a(100),
+		.c_depth_b(100),
+		.c_enable_rlocs(0),
+		.c_has_default_data(0),
+		.c_has_dina(0),
+		.c_has_dinb(0),
+		.c_has_douta(1),
+		.c_has_doutb(1),
+		.c_has_ena(0),
+		.c_has_enb(0),
+		.c_has_limit_data_pitch(0),
+		.c_has_nda(0),
+		.c_has_ndb(0),
+		.c_has_rdya(0),
+		.c_has_rdyb(0),
+		.c_has_rfda(0),
+		.c_has_rfdb(0),
+		.c_has_sinita(0),
+		.c_has_sinitb(0),
+		.c_has_wea(0),
+		.c_has_web(0),
+		.c_limit_data_pitch(18),
+		.c_mem_init_file("Binary_to_Decimal.mif"),
+		.c_pipe_stages_a(0),
+		.c_pipe_stages_b(0),
+		.c_reg_inputsa(0),
+		.c_reg_inputsb(0),
+		.c_sim_collision_check("NONE"),
+		.c_sinita_value("0"),
+		.c_sinitb_value("0"),
+		.c_width_a(8),
+		.c_width_b(8),
+		.c_write_modea(0),
+		.c_write_modeb(0),
+		.c_ybottom_addr("0"),
+		.c_yclka_is_rising(1),
+		.c_yclkb_is_rising(1),
+		.c_yena_is_high(1),
+		.c_yenb_is_high(1),
+		.c_yhierarchy("hierarchy1"),
+		.c_ymake_bmm(0),
+		.c_yprimitive_type("16kx1"),
+		.c_ysinita_is_high(1),
+		.c_ysinitb_is_high(1),
+		.c_ytop_addr("1024"),
+		.c_yuse_single_primitive(0),
+		.c_ywea_is_high(1),
+		.c_yweb_is_high(1),
+		.c_yydisable_warnings(1))
+	inst (
+		.ADDRA(addra),
+		.ADDRB(addrb),
+		.CLKA(clka),
+		.CLKB(clkb),
+		.DOUTA(douta),
+		.DOUTB(doutb),
+		.DINA(),
+		.DINB(),
+		.ENA(),
+		.ENB(),
+		.NDA(),
+		.NDB(),
+		.RFDA(),
+		.RFDB(),
+		.RDYA(),
+		.RDYB(),
+		.SINITA(),
+		.SINITB(),
+		.WEA(),
+		.WEB());
+
+
+// synthesis translate_on
+
+// XST black box declaration
+// box_type "black_box"
+// synthesis attribute box_type of Binary_to_Decimal is "black_box"
+
+endmodule
+
diff --git a/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.veo b/UI/UI Interfaces/Binary to Decimal ROM/Binary_to_Decimal.veo
@@ -0,0 +1,48 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+Binary_to_Decimal YourInstanceName (
+	.addra(addra), // Bus [6 : 0] 
+	.addrb(addrb), // Bus [6 : 0] 
+	.clka(clka),
+	.clkb(clkb),
+	.douta(douta), // Bus [7 : 0] 
+	.doutb(doutb)); // Bus [7 : 0] 
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file Binary_to_Decimal.v when simulating
+// the core, Binary_to_Decimal. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+