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kientuong114/Progetto_Reti_Logiche_2019

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Prova Finale di Reti Logiche 2019

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This repo contains my submission for the 2019 Digital Circuit Design project at Politecnico di Milano.

The component required had to receive a 8-bit address as input and encode it by following the specifications in "Working-zone encoding for redcuing the energy in microprocessor address buses" by E. Musoll, T. Lang and J. Cortadella.

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Digital Circuit Design project for Politecnico di Milano

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