re-add the older 'unoptimized' debouncer for later

processor.xise

@@ -330,7 +330,7 @@
     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="E:/Xilinx/14.6/ISE_DS/ISE/spartan6/data/spartan6_runtime.xds" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="E:/Xilinx/14.6/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
     <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>

src/util.v

@@ -102,3 +102,25 @@ module debounce #(parameter B=16) (
 		end
 	end
 endmodule
+
+module debounce_unopt #(parameter N=100000) (
+		input wire clk,
+		input wire in,
+		output reg out
+	);
+
+	reg prev;
+	reg [16:0] ctr;
+	reg _o; // pipeline register for out
+	always @(posedge clk) begin
+		if (in != prev) begin
+			prev <= in;
+			ctr <= 0;
+		end else if (ctr == N) begin
+			_o <= in;
+		end else begin
+			ctr <= ctr + 1;
+		end
+		out <= _o;
+	end
+endmodule