ASoC: intel: board: sof_rt5682: Update rt1015 pll input clk freq

In commit d696a61 ("ASoC: rt1015: Add condition to prevent SoC
providing bclk in ratio of 50 times of sample rate."), PLL input at 50fs
is no longer supported, the new recommended settings at 48Khz rate are:

PLL input       SSP bclk
------------------------
64fs            3.073Mhz
100fs           4.8Mhz

(bclk update is reflected in topoplogy.)

Signed-off-by: Yong Zhi <yong.zhi@intel.com>

sound/soc/intel/boards/sof_rt5682.c

@@ -284,8 +284,15 @@ static int sof_rt1015_hw_params(struct snd_pcm_substream *substream,
 		return 0;
 
 	for_each_rtd_codec_dais(rtd, i, codec_dai) {
+		/* Set tdm/i2s1 master bclk ratio */
+		ret = snd_soc_dai_set_bclk_ratio(codec_dai, 64);
+		if (ret < 0) {
+			dev_err(card->dev, "failed to set bclk ratio\n");
+			return ret;
+		}
+
 		ret = snd_soc_dai_set_pll(codec_dai, 0, RT1015_PLL_S_BCLK,
-					  params_rate(params) * 50,
+					  params_rate(params) * 64,
 					  params_rate(params) * 256);
 		if (ret < 0) {
 			dev_err(card->dev, "failed to set pll\n");