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changed polarity of ASIC
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cwfletcher committed Oct 16, 2014
1 parent 98cf904 commit efa13f2
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Showing 39 changed files with 3,274 additions and 3,256 deletions.
574 changes: 287 additions & 287 deletions TinyORAMCore.v

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2 changes: 1 addition & 1 deletion addr/AddrGen.v
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ module AddrGen
reg RW, BH;
reg [BBSTWidth-1:0] BktCounter;

`ifdef ASIC
`ifndef FPGA
AddrGenBktHead
abt ( .Clock( Clock),
.Reset( Reset),
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2 changes: 1 addition & 1 deletion addr/AddrGenBktHead.v
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ module AddrGenBktHead
output [ORAML:0] STIdx, BktIdxInST; // tmp output for debugging


`ifndef ASIC
`ifdef FPGA
initial begin // don't delete, REWAES needs this to get rid of Reset
currentLevel = ORAML+1;
end
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4 changes: 2 additions & 2 deletions backend/BackendCoreController.v
Original file line number Diff line number Diff line change
Expand Up @@ -169,7 +169,7 @@ module BackendCoreController(
Register #( .Width(1), .Initial(1'b0))
first_access (Clock, Reset, CommandRequest, 1'b0, 1'bx, OneAccessHasOccurred);

`ifndef ASIC
`ifdef FPGA
initial begin
CS = ST_Idle;
end
Expand Down Expand Up @@ -359,7 +359,7 @@ module BackendCoreController(

assign DummyLeaf = DummyLeaf_Pre;

`ifndef ASIC
`ifdef FPGA
initial begin
ROPAddr = {ORAMU{1'bx}};
ROLeaf = {ORAML{1'bx}};
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6 changes: 3 additions & 3 deletions backend/PathORAMBackend.v
Original file line number Diff line number Diff line change
Expand Up @@ -287,7 +287,7 @@ module PathORAMBackend(

.ORAMUValid( ORAMUValid))
bend_core( .Clock( Clock),
`ifdef ASIC
`ifndef FPGA
.Reset( Reset),
`else
.Reset( 1'b0),
Expand Down Expand Up @@ -347,7 +347,7 @@ module PathORAMBackend(
.ORAMUValid( ORAMUValid))
aes( .Clock( Clock),
.FastClock( AESClock),
`ifdef ASIC
`ifndef FPGA
.Reset( Reset),
`else
.Reset( 1'b0),
Expand Down Expand Up @@ -382,7 +382,7 @@ module PathORAMBackend(
.FEDWidth( FEDWidth),
.BEDWidth( BEDWidth))
aes( .Clock( Clock),
`ifdef ASIC
`ifndef FPGA
.Reset( Reset),
`else
.Reset( 1'b0),
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