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chipset_enable.c
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chipset_enable.c
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/*
* This file is part of the flashrom project.
*
* Copyright (C) 2000 Silicon Integrated System Corporation
* Copyright (C) 2005-2009 coresystems GmbH
* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
* Copyright (C) 2009 Kontron Modular Computers GmbH
* Copyright (C) 2011, 2012 Stefan Tauner
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* Contains the chipset specific flash enables.
*/
#define _LARGEFILE64_SOURCE
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <inttypes.h>
#include <errno.h>
#include "flash.h"
#include "programmer.h"
#include "hwaccess.h"
#define NOT_DONE_YET 1
#if defined(__i386__) || defined(__x86_64__)
static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
/*
* ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
* 0xFFFE0000-0xFFFFFFFF ROM select enable.
*/
tmp = pci_read_byte(dev, 0x47);
tmp |= 0x46;
rpci_write_byte(dev, 0x47, tmp);
return 0;
}
static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
/* enable ROMCS for writes */
tmp = pci_read_byte(dev, 0x43);
tmp |= 0x80;
pci_write_byte(dev, 0x43, tmp);
/* read the bootstrapping register */
tmp = pci_read_byte(dev, 0x40) & 0x3;
switch (tmp) {
case 3:
internal_buses_supported = BUS_FWH;
break;
case 2:
internal_buses_supported = BUS_LPC;
break;
default:
internal_buses_supported = BUS_PARALLEL;
break;
}
return 0;
}
static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
tmp = pci_read_byte(dev, 0xd0);
tmp |= 0xf8;
rpci_write_byte(dev, 0xd0, tmp);
return 0;
}
static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
{
#define SIS_MAPREG 0x40
uint8_t new, newer;
/* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
/* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
new = pci_read_byte(dev, SIS_MAPREG);
new &= (~0x04); /* No idea why we clear bit 2. */
new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
rpci_write_byte(dev, SIS_MAPREG, new);
newer = pci_read_byte(dev, SIS_MAPREG);
if (newer != new) { /* FIXME: share this with other code? */
msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
SIS_MAPREG, new, name);
msg_pinfo("Stuck at 0x%02x.\n", newer);
return -1;
}
return 0;
}
static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
{
struct pci_dev *sbdev;
sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
if (!sbdev)
sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
if (!sbdev)
sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
if (!sbdev)
msg_perr("No southbridge found for %s!\n", name);
if (sbdev)
msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
sbdev->vendor_id, sbdev->device_id,
sbdev->bus, sbdev->dev, sbdev->func);
return sbdev;
}
static int enable_flash_sis501(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
int ret = 0;
struct pci_dev *sbdev;
sbdev = find_southbridge(dev->vendor_id, name);
if (!sbdev)
return -1;
ret = enable_flash_sis_mapping(sbdev, name);
tmp = sio_read(0x22, 0x80);
tmp &= (~0x20);
tmp |= 0x4;
sio_write(0x22, 0x80, tmp);
tmp = sio_read(0x22, 0x70);
tmp &= (~0x20);
tmp |= 0x4;
sio_write(0x22, 0x70, tmp);
return ret;
}
static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
int ret = 0;
struct pci_dev *sbdev;
sbdev = find_southbridge(dev->vendor_id, name);
if (!sbdev)
return -1;
ret = enable_flash_sis_mapping(sbdev, name);
tmp = sio_read(0x22, 0x50);
tmp &= (~0x20);
tmp |= 0x4;
sio_write(0x22, 0x50, tmp);
return ret;
}
static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask)
{
#define SIS_REG 0x45
uint8_t new, newer;
int ret = 0;
struct pci_dev *sbdev;
sbdev = find_southbridge(dev->vendor_id, name);
if (!sbdev)
return -1;
ret = enable_flash_sis_mapping(sbdev, name);
new = pci_read_byte(sbdev, SIS_REG);
new &= (~dis_mask);
new |= en_mask;
rpci_write_byte(sbdev, SIS_REG, new);
newer = pci_read_byte(sbdev, SIS_REG);
if (newer != new) { /* FIXME: share this with other code? */
msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name);
msg_pinfo("Stuck at 0x%02x\n", newer);
ret = -1;
}
return ret;
}
static int enable_flash_sis530(struct pci_dev *dev, const char *name)
{
return enable_flash_sis5x0(dev, name, 0x20, 0x04);
}
static int enable_flash_sis540(struct pci_dev *dev, const char *name)
{
return enable_flash_sis5x0(dev, name, 0x80, 0x40);
}
/* Datasheet:
* - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
* - URL: http://www.intel.com/design/intarch/datashts/290562.htm
* - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
* - Order Number: 290562-001
*/
static int enable_flash_piix4(struct pci_dev *dev, const char *name)
{
uint16_t old, new;
uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
internal_buses_supported = BUS_PARALLEL;
old = pci_read_word(dev, xbcs);
/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
* FFF00000-FFF7FFFF are forwarded to ISA).
* Note: This bit is reserved on PIIX/PIIX3/MPIIX.
* Set bit 7: Extended BIOS Enable (PCI master accesses to
* FFF80000-FFFDFFFF are forwarded to ISA).
* Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
* the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
* of 1 Mbyte, or the aliases at the top of 4 Gbyte
* (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
* Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
* Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
*/
if (dev->device_id == 0x122e || dev->device_id == 0x7000
|| dev->device_id == 0x1234)
new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
else
new = old | 0x02c4;
if (new == old)
return 0;
rpci_write_word(dev, xbcs, new);
if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */
msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name);
return -1;
}
return 0;
}
/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space
* at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'.
*
* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom
* chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */
static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr,
struct pci_dev *dev, uint8_t bios_cntl)
{
uint8_t old, new, wanted;
switch (ich_generation) {
case CHIPSET_ICH_UNKNOWN:
return ERROR_FATAL;
/* Non-SPI-capable */
case CHIPSET_ICH:
case CHIPSET_ICH2345:
break;
/* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to
* what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register.
* The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it
* mentions that the prefetching and caching does only happen for direct memory reads.
* Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the
* programmed access only and not memory mapping. */
case CHIPSET_TUNNEL_CREEK:
case CHIPSET_POULSBO:
case CHIPSET_CENTERTON:
old = pci_read_byte(dev, bios_cntl + 1);
msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
break;
case CHIPSET_BAYTRAIL:
case CHIPSET_ICH7:
default: /* Future version might behave the same */
if (ich_generation == CHIPSET_BAYTRAIL)
old = (mmio_readl(addr) >> 2) & 0x3;
else
old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3;
msg_pdbg("SPI Read Configuration: ");
if (old == 3)
msg_pdbg("invalid prefetching/caching settings, ");
else
msg_pdbg("prefetching %sabled, caching %sabled, ",
(old & 0x2) ? "en" : "dis",
(old & 0x1) ? "dis" : "en");
}
if (ich_generation == CHIPSET_BAYTRAIL)
wanted = old = mmio_readl(addr);
else
wanted = old = pci_read_byte(dev, bios_cntl);
/*
* Quote from the 6 Series datasheet (Document Number: 324645-004):
* "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
* 1 = BIOS region SMM protection is enabled.
* The BIOS Region is not writable unless all processors are in SMM."
* In earlier chipsets this bit is reserved.
*
* Try to unset it in any case.
* It won't hurt and makes sense in some cases according to Stefan Reinauer.
*
* At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom
* and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway.
*/
int smm_bwp_bit;
if (ich_generation == CHIPSET_CENTERTON)
smm_bwp_bit = 7;
else
smm_bwp_bit = 5;
wanted &= ~(1 << smm_bwp_bit);
/* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */
if (ich_generation == CHIPSET_TUNNEL_CREEK)
wanted |= (1 << 2);
wanted |= (1 << 0); /* Set BIOS Write Enable */
wanted &= ~(1 << 1); /* Disable lock (futile) */
/* Only write the register if it's necessary */
if (wanted != old) {
if (ich_generation == CHIPSET_BAYTRAIL) {
rmmio_writel(wanted, addr);
new = mmio_readl(addr);
} else {
rpci_write_byte(dev, bios_cntl, wanted);
new = pci_read_byte(dev, bios_cntl);
}
} else
new = old;
msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new);
msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis");
msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis");
if (new & (1 << smm_bwp_bit))
msg_pwarn("Warning: BIOS region SMM protection is enabled!\n");
if (new != wanted)
msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x failed.\n"
"New value is 0x%02x.\n", bios_cntl, old, wanted, new);
/* Return an error if we could not set the write enable only. */
if (!(new & (1 << 0)))
return -1;
return 0;
}
static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation,
uint8_t bios_cntl)
{
return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl);
}
static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr)
{
return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0);
}
static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation)
{
uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */
bool implemented = 0;
void *ilb = NULL; /* Only for Baytrail */
switch (ich_generation) {
case CHIPSET_ICH:
/* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB
* and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */
break;
case CHIPSET_ICH2345:
fwh_sel1 = 0xe8;
fwh_sel2 = 0xee;
fwh_dec_en_lo = 0xf0;
fwh_dec_en_hi = 0xe3;
implemented = 1;
break;
case CHIPSET_POULSBO:
case CHIPSET_TUNNEL_CREEK:
/* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each,
* FWH_DEC_EN (D7h) and FWH_SEL (D0h). */
break;
case CHIPSET_CENTERTON:
/* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */
break;
case CHIPSET_BAYTRAIL: {
uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */
if (ilb_base == 0) {
msg_perr("Error: Invalid ILB_BASE_ADDRESS\n");
return ERROR_FATAL;
}
ilb = rphysmap("BYT IBASE", ilb_base, 512);
fwh_sel1 = 0x18;
fwh_dec_en_lo = 0xd8;
fwh_dec_en_hi = 0xd9;
implemented = 1;
break;
}
case CHIPSET_ICH6:
case CHIPSET_ICH7:
default: /* Future version might behave the same */
fwh_sel1 = 0xd0;
fwh_sel2 = 0xd4;
fwh_dec_en_lo = 0xd8;
fwh_dec_en_hi = 0xd9;
implemented = 1;
break;
}
char *idsel = extract_programmer_param("fwh_idsel");
if (idsel && strlen(idsel)) {
if (!implemented) {
msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n");
goto idsel_garbage_out;
}
errno = 0;
/* Base 16, nothing else makes sense. */
uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
if (errno) {
msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n");
goto idsel_garbage_out;
}
uint64_t fwh_mask = 0xffffffff;
if (fwh_sel2 > 0)
fwh_mask |= (0xffffULL << 32);
if (fwh_idsel & ~fwh_mask) {
msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n");
goto idsel_garbage_out;
}
uint64_t fwh_idsel_old;
if (ich_generation == CHIPSET_BAYTRAIL) {
fwh_idsel_old = mmio_readl(ilb + fwh_sel1);
rmmio_writel(fwh_idsel, ilb + fwh_sel1);
} else {
fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16;
rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff);
if (fwh_sel2 > 0) {
fwh_idsel_old |= pci_read_word(dev, fwh_sel2);
rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff);
}
}
msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n",
fwh_idsel_old, fwh_idsel);
/* FIXME: Decode settings are not changed. */
} else if (idsel) {
msg_perr("Error: fwh_idsel= specified, but no value given.\n");
idsel_garbage_out:
free(idsel);
return ERROR_FATAL;
}
free(idsel);
if (!implemented) {
msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n");
return 0;
}
/* Ignore all legacy ranges below 1 MB.
* We currently only support flashing the chip which responds to
* IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
* have to be adjusted.
*/
int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
bool contiguous = 1;
uint32_t fwh_conf;
if (ich_generation == CHIPSET_BAYTRAIL)
fwh_conf = mmio_readl(ilb + fwh_sel1);
else
fwh_conf = pci_read_long(dev, fwh_sel1);
int i;
/* FWH_SEL1 */
for (i = 7; i >= 0; i--) {
int tmp = (fwh_conf >> (i * 4)) & 0xf;
msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
(0x1ff8 + i) * 0x80000,
(0x1ff0 + i) * 0x80000,
tmp);
if ((tmp == 0) && contiguous) {
max_decode_fwh_idsel = (8 - i) * 0x80000;
} else {
contiguous = 0;
}
}
if (fwh_sel2 > 0) {
/* FWH_SEL2 */
fwh_conf = pci_read_word(dev, fwh_sel2);
for (i = 3; i >= 0; i--) {
int tmp = (fwh_conf >> (i * 4)) & 0xf;
msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
(0xff4 + i) * 0x100000,
(0xff0 + i) * 0x100000,
tmp);
if ((tmp == 0) && contiguous) {
max_decode_fwh_idsel = (8 - i) * 0x100000;
} else {
contiguous = 0;
}
}
}
contiguous = 1;
/* FWH_DEC_EN1 */
fwh_conf = pci_read_byte(dev, fwh_dec_en_hi);
fwh_conf <<= 8;
fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo);
for (i = 7; i >= 0; i--) {
int tmp = (fwh_conf >> (i + 0x8)) & 0x1;
msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
(0x1ff8 + i) * 0x80000,
(0x1ff0 + i) * 0x80000,
tmp ? "en" : "dis");
if ((tmp == 1) && contiguous) {
max_decode_fwh_decode = (8 - i) * 0x80000;
} else {
contiguous = 0;
}
}
for (i = 3; i >= 0; i--) {
int tmp = (fwh_conf >> i) & 0x1;
msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
(0xff4 + i) * 0x100000,
(0xff0 + i) * 0x100000,
tmp ? "en" : "dis");
if ((tmp == 1) && contiguous) {
max_decode_fwh_decode = (8 - i) * 0x100000;
} else {
contiguous = 0;
}
}
max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh);
return 0;
}
static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
{
int err;
/* Configure FWH IDSEL decoder maps. */
if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0)
return err;
internal_buses_supported = BUS_FWH;
return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl);
}
static int enable_flash_ich0(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e);
}
static int enable_flash_ich2345(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e);
}
static int enable_flash_ich6(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc);
}
static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8);
}
static void enable_flash_ich_handle_gcs(struct pci_dev *dev, enum ich_chipset ich_generation, uint32_t gcs, bool top_swap)
{
msg_pdbg("GCS = 0x%x: ", gcs);
msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis");
static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" };
static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" };
static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" };
static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" };
static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" };
static const char *const straps_names_pch89_baytrail[] = { "LPC", "reserved", "reserved", "SPI" };
static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" };
static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" };
const char *const *straps_names;
switch (ich_generation) {
case CHIPSET_ICH7:
/* EP80579 may need further changes, but this is the least
* intrusive way to get correct BOOT Strap printing without
* changing the rest of its code path). */
if (dev->device_id == 0x5031)
straps_names = straps_names_EP80579;
else
straps_names = straps_names_ich7_nm10;
break;
case CHIPSET_ICH8:
case CHIPSET_ICH9:
case CHIPSET_ICH10:
straps_names = straps_names_ich8910;
break;
case CHIPSET_TUNNEL_CREEK:
straps_names = straps_names_tunnel_creek;
break;
case CHIPSET_5_SERIES_IBEX_PEAK:
case CHIPSET_6_SERIES_COUGAR_POINT:
case CHIPSET_7_SERIES_PANTHER_POINT:
straps_names = straps_names_pch567;
break;
case CHIPSET_8_SERIES_LYNX_POINT:
case CHIPSET_9_SERIES_WILDCAT_POINT:
case CHIPSET_BAYTRAIL:
straps_names = straps_names_pch89_baytrail;
break;
case CHIPSET_8_SERIES_LYNX_POINT_LP:
straps_names = straps_names_pch8_lp;
break;
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all
straps_names = straps_names_unknown;
break;
default:
msg_gerr("%s: unknown ICH generation. Please report!\n", __func__);
straps_names = straps_names_unknown;
break;
}
uint8_t bbs;
switch (ich_generation) {
case CHIPSET_TUNNEL_CREEK:
bbs = (gcs >> 1) & 0x1;
break;
case CHIPSET_8_SERIES_LYNX_POINT_LP:
/* Lynx Point LP uses a single bit for BBS */
bbs = (gcs >> 10) & 0x1;
break;
default:
/* Other chipsets use two bits for BBS */
bbs = (gcs >> 10) & 0x3;
break;
}
msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
/* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */
if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON)
msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled");
}
static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
{
/* Get physical address of Root Complex Register Block */
uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000;
msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra);
/* Map RCBA to virtual memory */
void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000);
if (rcrb == ERROR_PTR)
return ERROR_FATAL;
enable_flash_ich_handle_gcs(dev, ich_generation, mmio_readl(rcrb + 0x3410), mmio_readb(rcrb + 0x3414));
/* Handle FWH-related parameters and initialization */
int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl);
if (ret_fwh == ERROR_FATAL)
return ret_fwh;
/* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */
uint16_t spibar_offset;
switch (ich_generation) {
case CHIPSET_BAYTRAIL:
case CHIPSET_ICH_UNKNOWN:
return ERROR_FATAL;
case CHIPSET_ICH7:
case CHIPSET_ICH8:
case CHIPSET_TUNNEL_CREEK:
case CHIPSET_CENTERTON:
spibar_offset = 0x3020;
break;
case CHIPSET_ICH9:
default: /* Future version might behave the same */
spibar_offset = 0x3800;
break;
}
msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset);
void *spibar = rcrb + spibar_offset;
/* This adds BUS_SPI */
int ret_spi = ich_init_spi(dev, spibar, ich_generation);
if (ret_spi == ERROR_FATAL)
return ret_spi;
if (ret_fwh || ret_spi)
return ERROR_NONFATAL;
return 0;
}
static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8);
}
static int enable_flash_s12x0(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8);
}
static int enable_flash_ich7(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc);
}
static int enable_flash_ich8(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc);
}
static int enable_flash_ich9(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc);
}
static int enable_flash_ich10(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc);
}
/* Ibex Peak aka. 5 series & 3400 series */
static int enable_flash_pch5(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc);
}
/* Cougar Point aka. 6 series & c200 series */
static int enable_flash_pch6(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc);
}
/* Panther Point aka. 7 series */
static int enable_flash_pch7(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc);
}
/* Lynx Point aka. 8 series */
static int enable_flash_pch8(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc);
}
/* Lynx Point LP aka. 8 series low-power */
static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc);
}
/* Wellsburg (for Haswell-EP Xeons) */
static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc);
}
/* Wildcat Point */
static int enable_flash_pch9(struct pci_dev *dev, const char *name)
{
return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
}
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
* These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
*
* Differences include:
* - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB.
* - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410).
* - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414).
* - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800).
* - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC).
*/
static int enable_flash_silvermont(struct pci_dev *dev, const char *name)
{
enum ich_chipset ich_generation = CHIPSET_BAYTRAIL;
/* Get physical address of Root Complex Register Block */
uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00;
msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba);
/* Handle GCS (in RCRB) */
void *rcrb = physmap("BYT RCRB", rcba, 4);
uint32_t gcs = mmio_readl(rcrb + 0);
enable_flash_ich_handle_gcs(dev, ich_generation, gcs, gcs & 0x2);
physunmap(rcrb, 4);
/* Handle fwh_idsel parameter */
int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation);
if (ret_fwh == ERROR_FATAL)
return ret_fwh;
internal_buses_supported = BUS_FWH;
/* Get physical address of SPI Base Address and map it */
uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
/* Enable Flash Writes.
* Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).
*/
enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC);
int ret_spi = ich_init_spi(dev, spibar, ich_generation);
if (ret_spi == ERROR_FATAL)
return ret_spi;
if (ret_fwh || ret_spi)
return ERROR_NONFATAL;
return 0;
}
static int via_no_byte_merge(struct pci_dev *dev, const char *name)
{
uint8_t val;
val = pci_read_byte(dev, 0x71);
if (val & 0x40) {
msg_pdbg("Disabling byte merging\n");
val &= ~0x40;
rpci_write_byte(dev, 0x71, val);
}
return NOT_DONE_YET; /* need to find south bridge, too */
}
static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
{
uint8_t val;
/* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
rpci_write_byte(dev, 0x41, 0x7f);
/* ROM write enable */
val = pci_read_byte(dev, 0x40);
val |= 0x10;
rpci_write_byte(dev, 0x40, val);
if (pci_read_byte(dev, 0x40) != val) {
msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name);
return -1;
}
if (dev->device_id == 0x3227) { /* VT8237/VT8237R */
/* All memory cycles, not just ROM ones, go to LPC. */
val = pci_read_byte(dev, 0x59);
val &= ~0x80;
rpci_write_byte(dev, 0x59, val);
}
return 0;
}
static int enable_flash_vt_vx(struct pci_dev *dev, const char *name)
{
struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353);
if (south_north == NULL) {
msg_perr("Could not find South-North Module Interface Control device!\n");
return ERROR_FATAL;
}
msg_pdbg("Strapped to ");
if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) {
msg_pdbg("LPC.\n");
return enable_flash_vt823x(dev, name);
}
msg_pdbg("SPI.\n");
uint32_t mmio_base;
void *mmio_base_physmapped;
uint32_t spi_cntl;
#define SPI_CNTL_LEN 0x08
uint32_t spi0_mm_base = 0;
switch(dev->device_id) {
case 0x8353: /* VX800/VX820 */
spi0_mm_base = pci_read_long(dev, 0xbc) << 8;
break;
case 0x8409: /* VX855/VX875 */
case 0x8410: /* VX900 */
mmio_base = pci_read_long(dev, 0xbc) << 8;
mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN);
if (mmio_base_physmapped == ERROR_PTR)
return ERROR_FATAL;
/* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */
spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00;
if ((spi_cntl & 0x01) == 0) {
msg_pdbg ("SPI Bus0 disabled!\n");
physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
return ERROR_FATAL;
}
/* Offset 1-3 has SPI Bus Memory Map Base Address: */
spi0_mm_base = spi_cntl & 0xFFFFFF00;
/* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */
spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04;
if ((spi_cntl & 0x01) == 1)
msg_pdbg2("SPI Bus1 is enabled too.\n");
physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
break;
default:
msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id);
return ERROR_FATAL;
}
return via_init_spi(dev, spi0_mm_base);
}
static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
{
return via_init_spi(dev, pci_read_long(dev, 0xbc) << 8);
}
static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
{
uint8_t reg8;
#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
#define ROM_WRITE_ENABLE (1 << 1)
#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
#define CS5530_ISA_MASTER (1 << 7)
#define CS5530_ENABLE_SA2320 (1 << 2)
#define CS5530_ENABLE_SA20 (1 << 6)
internal_buses_supported = BUS_PARALLEL;
/* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
* FIXME: Should we really touch the low mapping below 1 MB? Flashrom
* ignores that region completely.
* Make the configured ROM areas writable.
*/
reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
reg8 |= LOWER_ROM_ADDRESS_RANGE;
reg8 |= UPPER_ROM_ADDRESS_RANGE;
reg8 |= ROM_WRITE_ENABLE;
rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
/* Set positive decode on ROM. */
reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
reg8 |= BIOS_ROM_POSITIVE_DECODE;
rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
if (reg8 & CS5530_ISA_MASTER) {
/* We have A0-A23 available. */
max_rom_decode.parallel = 16 * 1024 * 1024;
} else {
reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
if (reg8 & CS5530_ENABLE_SA2320) {
/* We have A0-19, A20-A23 available. */
max_rom_decode.parallel = 16 * 1024 * 1024;
} else if (reg8 & CS5530_ENABLE_SA20) {
/* We have A0-19, A20 available. */
max_rom_decode.parallel = 2 * 1024 * 1024;
} else {
/* A20 and above are not active. */
max_rom_decode.parallel = 1024 * 1024;
}
}
return 0;
}
/*
* Geode systems write protect the BIOS via RCONFs (cache settings similar
* to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
*
* Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
* To enable write to NOR Boot flash for the benefit of systems that have such
* a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).