Merge e4811fc into e115690

leonardt · May 15, 2019 · 3d8081b · 3d8081b
2 parents e115690 + e4811fc
commit 3d8081b
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Showing 3 changed files with 21 additions and 13 deletions.
diff --git a/fault/system_verilog_target.py b/fault/system_verilog_target.py
@@ -12,7 +12,6 @@
 
 src_tpl = """\
 module {circuit_name}_tb;
-integer __error_occurred = 0;
 {declarations}
 
     {circuit_name} dut (
@@ -21,12 +20,7 @@
 
     initial begin
 {initial_body}
-        #20 begin
-            if (__error_occurred)
-                $stop;
-            else
-                $finish;
-        end;
+        #20 $finish;
     end
 
 endmodule
@@ -60,7 +54,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/",
 
         magma_opts: Options dictionary for `magma.compile` command
 
-        simulator: "ncsim" or "vcs"
+        simulator: "ncsim", "vcs", or "iverilog"
 
         timescale: Set the timescale for the verilog simulation
                    (default 1ns/1ns)
@@ -190,7 +184,6 @@ def make_expect(self, i, action):
         return f"""
 if ({name} != {value}) begin
     $error(\"Failed on action={i} checking port {debug_name}. Expected %x, got %x\" , {value}, {name});
-    __error_occurred |= 1;
 end;
 """.splitlines()  # noqa
 
@@ -289,8 +282,7 @@ def run(self, actions):
         print(f"Running command: {cmd}")
         assert not subprocess.call(cmd, cwd=self.directory, shell=True)
         if self.simulator == "vcs":
-            print(f"Running command: {cmd}")
-            assert not subprocess.call("./simv", cwd=self.directory, shell=True)
+            assert not subprocess.call("./simv | tee /dev/stdout | grep Error || exit 0 && exit 1", cwd=self.directory, shell=True)  # noqa
         elif self.simulator == "iverilog":
             assert not subprocess.call(f"vvp -N {self.circuit_name}_tb",
                                        cwd=self.directory, shell=True)
diff --git a/fault/verilator_target.py b/fault/verilator_target.py
@@ -376,8 +376,8 @@ def run(self, actions, verilator_includes=[], num_tests=0,
             self.circuit_name)
         assert not self.run_from_directory(verilator_make_cmd)
         assert not self.run_from_directory(
-            f"./obj_dir/V{self.circuit_name} | tee "
-            f"./obj_dir/{self.circuit_name}.log")
+            f"/bin/bash -c \"set -e -o pipefail; ./obj_dir/V{self.circuit_name}"
+            f" | tee ./obj_dir/{self.circuit_name}.log\"")
 
     def add_assumptions(self, circuit, actions, i):
         main_body = ""

diff --git a/tests/test_tester.py b/tests/test_tester.py
@@ -7,6 +7,7 @@
 import tempfile
 import os
 import shutil
+import pytest
 
 
 def pytest_generate_tests(metafunc):
@@ -56,6 +57,21 @@ def test_tester_basic(target, simulator):
     assert tester.actions == []
 
 
+@pytest.mark.xfail(strict=True)
+def test_tester_basic_fail(target, simulator):
+    circ = common.TestBasicCircuit
+    tester = fault.Tester(circ)
+    tester.zero_inputs()
+    tester.poke(circ.I, 1)
+    tester.eval()
+    tester.expect(circ.O, 0)
+    with tempfile.TemporaryDirectory() as _dir:
+        if target == "verilator":
+            tester.compile_and_run(target, directory=_dir, flags=["-Wno-fatal"])
+        else:
+            tester.compile_and_run(target, directory=_dir, simulator=simulator)
+
+
 def test_tester_clock(target, simulator):
     circ = common.TestPeekCircuit
     tester = fault.Tester(circ)