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import magma as m | ||
from fault import Tester | ||
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class PowerTester(Tester): | ||
def __init__(self, circuit: m.Circuit, clock: m.ClockType = None): | ||
super().__init__(circuit, clock) | ||
self.supply0s = [] | ||
self.supply1s = [] | ||
self.tris = [] | ||
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def add_power(self, port): | ||
self.supply1s.append(port.name.name) | ||
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def add_ground(self, port): | ||
self.supply0s.append(port.name.name) | ||
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def add_tri(self, port): | ||
self.tris.append(port.name.name) | ||
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def run(self, target="system-verilog"): | ||
power_args = { | ||
"supply0s": self.supply0s, | ||
"supply1s": self.supply1s, | ||
"tris": self.tris, | ||
} | ||
self.targets[target].run(self.actions, power_args) |
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import magma as m | ||
import mantle | ||
import fault | ||
from hwtypes import BitVector | ||
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def test_simple_alu_pd(): | ||
type_map = {"CLK": m.In(m.Clock)} | ||
circ = m.DefineFromVerilogFile("tests/verilog/simple_alu_pd.sv", | ||
type_map=type_map)[0] | ||
tester = fault.PowerTester(circ, circ.CLK) | ||
tester.add_power(circ.VDD_HIGH) | ||
tester.add_ground(circ.VSS) | ||
tester.add_tri(circ.VDD_HIGH_TOP_VIRTUAL) | ||
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tester.circuit.CLK = 0 | ||
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# Enable the power switch | ||
tester.circuit.config_addr = 0x00080000 | ||
tester.circuit.config_data = 0xFFFFFFF0 | ||
tester.circuit.config_en = 1 | ||
tester.step(2) | ||
tester.circuit.config_en = 0 | ||
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# rest of test... | ||
a, b = BitVector.random(16), BitVector.random(16) | ||
tester.circuit.a = a | ||
tester.circuit.b = b | ||
tester.circuit.c.expect(a + b) | ||
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# Disable the power switch | ||
tester.circuit.config_addr = 0x00080000 | ||
tester.circuit.config_data = 0xFFFFFFF0 | ||
tester.circuit.config_en = 1 | ||
tester.step(2) | ||
tester.circuit.config_en = 0 | ||
# Stall global signal should be on when tile is off | ||
tester.circuit.stall_out.expect(1) | ||
# reset signal should be on when tile is off | ||
tester.circuit.reset.expect(1) | ||
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# Enable the power switch | ||
tester.circuit.config_addr = 0x00080000 | ||
tester.circuit.config_data = 0xFFFFFFF0 | ||
tester.circuit.config_en = 1 | ||
tester.step(2) | ||
tester.circuit.config_en = 0 | ||
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# rest of test... | ||
a, b = BitVector.random(16), BitVector.random(16) | ||
tester.circuit.a = a | ||
tester.circuit.b = b | ||
tester.circuit.c.expect(a + b) | ||
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try: | ||
tester.compile_and_run(target="system-verilog", simulator="ncsim", | ||
directory="tests/build", skip_compile=True) | ||
except AssertionError: | ||
# Won't run because we don't have concrete DUT or ncsim, but we check | ||
# that the output has the right types for the special ports | ||
with open("tests/build/simple_alu_pd_tb.sv", "r") as f: | ||
for line in f.read().splitlines(): | ||
if "VDD_HIGH_TOP_VIRTUAL;" in line: | ||
assert line.lstrip().rstrip() == \ | ||
"tri VDD_HIGH_TOP_VIRTUAL;" | ||
elif "VDD_HIGH;" in line: | ||
assert line.lstrip().rstrip() == "supply1 VDD_HIGH;" | ||
elif "VSS;" in line: | ||
assert line.lstrip().rstrip() == "supply0 VSS;" |
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module simple_alu_pd(input [15:0] a, input [15:0] b, output [15:0] c, | ||
input [15:0] config_data, input [15:0] config_en, | ||
input CLK, input VDD_HIGH, input VSS, | ||
input VDD_HIGH_TOP_VIRTUAL, output stall_out, | ||
output reset); | ||
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// stub to test support for reading in modules with supply1, | ||
// supply0, and tri types | ||
endmodule |