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Merge 8a066c0 into 87e4a6a
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leonardt authored Aug 3, 2018
2 parents 87e4a6a + 8a066c0 commit 6e717cd
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Showing 8 changed files with 53 additions and 18 deletions.
1 change: 1 addition & 0 deletions fault/__init__.py
Original file line number Diff line number Diff line change
@@ -1 +1,2 @@
from .tester import Tester
from .values import AnyValue
17 changes: 16 additions & 1 deletion fault/python_simulator_target.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,8 @@
from .target import Target
from magma.simulator.python_simulator import PythonSimulator
from fault.array import Array
from bit_vector import BitVector
from fault.values import AnyValue


def convert_value(val):
Expand Down Expand Up @@ -30,7 +32,20 @@ def __check_value(self, port, expected_val):
f"is {expected_val}")
sim_val = self._simulator.get_value(port)
expected_val = convert_value(expected_val)
assert sim_val == expected_val
assert self.__check(sim_val, expected_val), \
f"Expected {expected_val}, got {sim_val}"

def __check(self, sim_val, expected_val):
if expected_val is AnyValue:
# Anything is equal to AnyValue
return True
if isinstance(sim_val, list):
if isinstance(expected_val, BitVector):
return expected_val.__class__(sim_val) == expected_val
assert isinstance(expected_val, list)
return all(self.__check(x, y)
for x, y in zip(sim_val, expected_val))
return sim_val == expected_val

def __parse_tv(self, tv):
inputs = {}
Expand Down
14 changes: 10 additions & 4 deletions fault/test_vectors.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
from magma import BitType, ArrayType, SIntType
from magma.simulator.python_simulator import PythonSimulator
from magma.bitutils import seq2int
from bit_vector import BitVector
from bit_vector import BitVector, SIntVector
from inspect import signature
from itertools import product
import pytest
Expand Down Expand Up @@ -81,7 +81,7 @@ def generate_simulator_test_vectors(circuit, input_ranges=None,
input_range = range(start, end)
else:
input_range = input_ranges[i]
args.append([BitVector(x, num_bits=num_bits, signed=True)
args.append([SIntVector(x, num_bits=num_bits)
for x in input_range])
else:
if input_ranges is None:
Expand All @@ -101,7 +101,10 @@ def generate_simulator_test_vectors(circuit, input_ranges=None,
for i, (name, port) in enumerate(circuit.interface.ports.items()):
# circuit defn output is an input to the idefinition
if port.isoutput():
testv[i] = test[j].as_int()
if isinstance(port, SIntType):
testv[i] = test[j].as_sint()
else:
testv[i] = test[j].as_uint()
val = test[j].as_bool_list()
if len(val) == 1:
val = val[0]
Expand All @@ -114,7 +117,10 @@ def generate_simulator_test_vectors(circuit, input_ranges=None,
# circuit defn input is an input of the definition
if port.isinput():
val = simulator.get_value(getattr(circuit, name))
val = BitVector(val, signed=isinstance(port, SIntType)).as_int()
if isinstance(port, SIntType):
val = SIntVector(val).as_sint()
else:
val = BitVector(val).as_uint()
testv[i] = val

tests.append(testv)
Expand Down
8 changes: 5 additions & 3 deletions fault/tester.py
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
import functools
from .verilator_target import VerilatorTarget
from fault.array import Array
from .values import AnyValue
import copy


Expand Down Expand Up @@ -38,15 +39,16 @@ def __init__(self, circuit, clock=None):

def get_initial_value(self, port):
if isinstance(port, m._BitType):
return BitVector(None, 1)
return AnyValue
elif isinstance(port, m.ArrayType):
return self.get_array_val(port)
else:
raise NotImplementedError(port)

def get_array_val(self, arr, val=None):
def get_array_val(self, arr, val=AnyValue):
if isinstance(arr.T, m._BitKind):
val = BitVector(val, len(arr))
if val is not AnyValue:
val = BitVector(val, len(arr))
elif isinstance(arr, m.ArrayType) and isinstance(arr.T, m.ArrayKind):
val = Array([self.get_array_val(x) for x in arr], len(arr))
else:
Expand Down
9 changes: 9 additions & 0 deletions fault/values.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
class __AnyValue:
"""
Used as an argument to expect when any value is allowed (e.g. wildcard,
don't care what the output value is)
"""
pass


AnyValue = __AnyValue()
15 changes: 8 additions & 7 deletions fault/verilator_target.py
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
import subprocess
import magma as m
from .array import Array
from .values import AnyValue


def flattened_names(arr):
Expand Down Expand Up @@ -41,14 +42,14 @@ def harness(circuit, tests):
typedef struct {{
unsigned int value;
bool is_x;
bool is_any_value;
}} value_t;
void check(const char* port, int a, value_t b, int i) {{
if (!b.is_x) {{
if (!b.is_any_value) {{
std::cerr << port << "=" << b.value << ", ";
}}
if (!b.is_x && !(a == b.value)) {{
if (!b.is_any_value && !(a == b.value)) {{
std::cerr << std::endl; // end the current line
std::cerr << \"Got : \" << a << std::endl;
std::cerr << \"Expected : \" << b.value << std::endl;
Expand All @@ -72,13 +73,13 @@ def harness(circuit, tests):
testvector = []

def to_string(t):
if t is None or t._value is None:
if t is AnyValue:
val = "0"
X = "true"
is_any_value = "true"
else:
val = t.as_binary_string()
X = "false"
return f"{{{val}, {X}}}"
is_any_value = "false"
return f"{{{val}, {is_any_value}}}"

for t in test:
if isinstance(t, Array):
Expand Down
1 change: 1 addition & 0 deletions requirements.txt
Original file line number Diff line number Diff line change
@@ -1,2 +1,3 @@
-e git://github.com/leonardt/bit_vector.git@int_vector#egg=bit_vector
-e git://github.com/phanrahan/magma.git#egg=magma
-e git://github.com/phanrahan/mantle.git#egg=mantle
6 changes: 3 additions & 3 deletions tests/test_tester.py
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ def test_tester_basic():
assert tester.test_vectors == [[BitVector(0, 1), BitVector(0, 1)]]
tester.eval()
assert tester.test_vectors == [[BitVector(0, 1), BitVector(0, 1)],
[BitVector(0, 1), BitVector(0, 1)]]
[BitVector(0, 1), fault.AnyValue]]


def test_tester_clock():
Expand All @@ -22,7 +22,7 @@ def test_tester_clock():
tester.poke(circ.I, 0)
tester.expect(circ.O, 0)
assert tester.test_vectors == [
[BitVector(0, 1), BitVector(0, 1), BitVector(None, 1)]
[BitVector(0, 1), BitVector(0, 1), fault.AnyValue]
]
tester.poke(circ.CLK, 0)
assert tester.test_vectors == [
Expand All @@ -31,7 +31,7 @@ def test_tester_clock():
tester.step()
assert tester.test_vectors == [
[BitVector(0, 1), BitVector(0, 1), BitVector(0, 1)],
[BitVector(0, 1), BitVector(0, 1), BitVector(1, 1)]
[BitVector(0, 1), fault.AnyValue, BitVector(1, 1)]
]


Expand Down

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