Merge a17e725 into e115690

fault/system_verilog_target.py

@@ -60,7 +60,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/",
 
         magma_opts: Options dictionary for `magma.compile` command
 
-        simulator: "ncsim" or "vcs"
+        simulator: "ncsim", "vcs", or "iverilog"
 
         timescale: Set the timescale for the verilog simulation
                    (default 1ns/1ns)

fault/verilator_target.py

@@ -376,8 +376,8 @@ def run(self, actions, verilator_includes=[], num_tests=0,
             self.circuit_name)
         assert not self.run_from_directory(verilator_make_cmd)
         assert not self.run_from_directory(
-            f"./obj_dir/V{self.circuit_name} | tee "
-            f"./obj_dir/{self.circuit_name}.log")
+            f"/bin/bash -c \"set -e -o pipefail; ./obj_dir/V{self.circuit_name}"
+            f" | tee ./obj_dir/{self.circuit_name}.log\"")
 
     def add_assumptions(self, circuit, actions, i):
         main_body = ""

tests/test_tester.py

@@ -7,6 +7,7 @@
 import tempfile
 import os
 import shutil
+import pytest
 
 
 def pytest_generate_tests(metafunc):
@@ -56,6 +57,21 @@ def test_tester_basic(target, simulator):
     assert tester.actions == []
 
 
+@pytest.mark.xfail(strict=True)
+def test_tester_basic_fail(target, simulator):
+    circ = common.TestBasicCircuit
+    tester = fault.Tester(circ)
+    tester.zero_inputs()
+    tester.poke(circ.I, 1)
+    tester.eval()
+    tester.expect(circ.O, 0)
+    with tempfile.TemporaryDirectory() as _dir:
+        if target == "verilator":
+            tester.compile_and_run(target, directory=_dir, flags=["-Wno-fatal"])
+        else:
+            tester.compile_and_run(target, directory=_dir, simulator=simulator)
+
+
 def test_tester_clock(target, simulator):
     circ = common.TestPeekCircuit
     tester = fault.Tester(circ)