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Original file line number | Diff line number | Diff line change |
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import fault.logging | ||
from .target import Target | ||
from magma.simulator.python_simulator import PythonSimulator | ||
from fault.array import Array | ||
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def convert_value(val): | ||
if isinstance(val, Array): | ||
return val.value | ||
return val | ||
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class PythonSimulatorTarget(Target): | ||
def __init__(self, circuit, test_vectors, clock): | ||
super().__init__(circuit, test_vectors) | ||
self._clock = clock | ||
self._simulator = None | ||
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def init_simulator(self): | ||
self._simulator = PythonSimulator(self._circuit, self._clock) | ||
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def __set_value(self, port, val): | ||
fault.logging.debug(f"Setting {self._circuit.name}.{port.name.name} to " | ||
f"{val}") | ||
val = convert_value(val) | ||
self._simulator.set_value(port, val) | ||
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def __check_value(self, port, expected_val): | ||
fault.logging.debug(f"Asserting {self._circuit.name}.{port.name.name} " | ||
f"is {expected_val}") | ||
sim_val = self._simulator.get_value(port) | ||
expected_val = convert_value(expected_val) | ||
assert sim_val == expected_val | ||
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def __parse_tv(self, tv): | ||
inputs = {} | ||
steps = 0 | ||
outputs = {} | ||
ports = self._circuit.interface.ports | ||
for i, port in enumerate(ports.values()): | ||
val = tv[i] | ||
if val is None: | ||
continue | ||
if port is self._clock: | ||
if self._simulator.get_value(self._clock) != val: | ||
steps += 1 | ||
elif port.isoutput(): | ||
inputs[port] = val | ||
elif port.isinput(): | ||
outputs[port] = val | ||
else: | ||
raise NotImplementedError() | ||
return (inputs, steps, outputs) | ||
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def __process_inputs(self, inputs): | ||
for port, val in inputs.items(): | ||
self.__set_value(port, val) | ||
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def __process_clock(self, steps): | ||
if steps == 0: | ||
return True | ||
self._simulator.advance(steps) | ||
return False | ||
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def __process_outputs(self, outputs): | ||
for port, val in outputs.items(): | ||
self.__check_value(port, val) | ||
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def run(self): | ||
self.init_simulator() | ||
ports = self._circuit.interface.ports | ||
test_vector_length = len(self._test_vectors[0]) | ||
assert len(ports.keys()) == test_vector_length | ||
for tv in self._test_vectors: | ||
(inputs, steps, outputs) = self.__parse_tv(tv) | ||
self.__process_inputs(inputs) | ||
evaluate = self.__process_clock(steps) | ||
if evaluate: | ||
self._simulator.evaluate() | ||
self.__process_outputs(outputs) |
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Original file line number | Diff line number | Diff line change |
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import random | ||
import magma as m | ||
import common | ||
from fault.python_simulator_target import * | ||
from bit_vector import BitVector | ||
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def test_python_simulator_target_basic(): | ||
""" | ||
Test basic python simuilator workflow with a simple circuit. | ||
""" | ||
circ = common.TestBasicCircuit | ||
test_vectors = [ | ||
[BitVector(0, 1), BitVector(0, 1)], | ||
[BitVector(1, 1), BitVector(1, 1)] | ||
] | ||
target = PythonSimulatorTarget(circ, test_vectors, None) | ||
target.run() | ||
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def test_python_simulator_target_nested_arrays(): | ||
circ = common.TestNestedArraysCircuit | ||
tester = fault.Tester(circ) | ||
for i in range(3): | ||
val = random.randint(0, (1 << 4) - 1) | ||
tester.poke(circ.I[i], val) | ||
tester.expect(circ.O[i], val) | ||
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target = PythonSimulatorTarget(circ, tester.test_vectors, None) | ||
target.run() | ||
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def test_python_simulator_target_clock(): | ||
circ = common.TestBasicClkCircuit | ||
test_vectors = [ | ||
[BitVector(0, 1), BitVector(0, 1), BitVector(0, 1)], | ||
[BitVector(0, 1), BitVector(0, 1), BitVector(1, 1)] | ||
] | ||
target = PythonSimulatorTarget(circ, test_vectors, circ.CLK) | ||
target.run() |