Use mlir verilog output

leonardt · Dec 7, 2023 · ff7d889 · ff7d889
1 parent e44b671
commit ff7d889
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/tests/test_tester/test_synchronous.py b/tests/test_tester/test_synchronous.py
@@ -33,7 +33,8 @@ def test_synchronous_basic(target, simulator):
 
     if target == "verilator":
         with tempfile.TemporaryDirectory(dir=".") as tempdir:
-            tester.compile_and_run("verilator", directory=tempdir)
+            tester.compile_and_run("verilator", directory=tempdir,
+                                   magma_output="mlir-verilog")
     else:
         tester.compile_and_run(target, simulator=simulator,
                                magma_opts={"sv": True})