Merge e6a3b32 into 1e530a1

verilog/counter.v

@@ -2,7 +2,7 @@ module vcounter(input CLK, output [2:0] O);
 reg [2:0] O;
 
 always @(posedge CLK) begin
-    O <= O + 1;
+    O <= O + 1'b1;
 end
 
 endmodule

verilog/detect111.v

@@ -3,7 +3,7 @@ module detect111(
   input I,
   output O
 );
-  reg [1:0] cnt = 0;
+  reg [1:0] cnt = 2'h0;
 
   wire [1:0] cnt_next;
 
@@ -12,8 +12,8 @@ module detect111(
   end
 
   // mealey version
-  assign cnt_next = I ? (cnt==3 ? cnt : cnt+1) : 0;
-  assign O = (cnt_next==3);
+  assign cnt_next = I ? (cnt==2'h3 ? cnt : cnt+1'b1) : 2'h0;
+  assign O = (cnt_next==2'h3);
   /* assign O = (cnt==3); */
 
 endmodule

verilog/dot.v

@@ -3,17 +3,17 @@ module vdot(input CLK, input I,
   reg [1:0] state;
   always @(posedge CLK) begin
     case (state)
-      0: begin
-        state <= I ? 1 : 0;
+      2'h0: begin
+        state <= I ? 2'h1 : 2'h0;
       end 
-      1: begin
-        state <= ~I ? 0 : 2;
+      2'h1: begin
+        state <= ~I ? 2'h0 : 2'h2;
       end
-      2: begin
-        state <= I ? 2 : 0;
+      2'h2: begin
+        state <= I ? 2'h2 : 2'h0;
       end
     endcase
   end
-  assign is_ = (state == 1) ? ~I : 0;
-  assign cb = (state == 0) ? I : 0;
+  assign is_ = (state == 2'h1) ? ~I : 1'b0;
+  assign cb = (state == 2'h0) ? I : 1'b0;
 endmodule

verilog/fifo.v

@@ -8,8 +8,8 @@ module fifo(
   output empty
 ); 
 
-  reg [2:0] waddr = 0;
-  reg [2:0] raddr = 0;
+  reg [2:0] waddr = 3'h0;
+  reg [2:0] raddr = 3'h0;
 
   reg [3:0] data [0:3];
 
@@ -19,11 +19,11 @@ module fifo(
   assign rvalid = ren & ~empty;
 
   always @(posedge CLK) begin
-    if (wvalid) waddr <= waddr+1;
+    if (wvalid) waddr <= waddr+1'b1;
   end
 
   always @(posedge CLK) begin
-    if (rvalid) raddr <= raddr+1;
+    if (rvalid) raddr <= raddr+1'b1;
   end
 
   always @(posedge CLK) begin

verilog/lbmem.v

@@ -11,37 +11,37 @@ module lbmem(
 
   reg [7:0] data [0:63];
 
-  reg state = 0;
+  reg state = 1'b0;
 
-  reg [4:0] cnt = 0;
+  reg [4:0] cnt = 5'h0;
 
   always @(posedge CLK) begin
-    if (state==0) begin
+    if (state==1'b0) begin
       cnt <= cnt + {3'h0,wen};
     end
     else begin
-      cnt <= wen ? cnt : cnt-1;
+      cnt <= wen ? cnt : cnt-1'b1;
     end
   end
 
   always @(posedge CLK) begin
-    if (state==0) begin
-      state <= (cnt==7 & wen); //cnt will be 8 on transition
+    if (state==1'b0) begin
+      state <= (cnt==5'h7 & wen); //cnt will be 8 on transition
     end
     else begin 
-      state <= (cnt!=1 | wen);
+      state <= (cnt!=5'h1 | wen);
     end
   end
-  assign valid = (state & (cnt!=1 | wen)) | (cnt == 7 & wen); 
+  assign valid = (state & (cnt!=5'h1 | wen)) | (cnt == 5'h7 & wen); 
 
-  reg [5:0] waddr = 0;
+  reg [5:0] waddr = 6'h0;
   wire [5:0] raddr;
-  assign raddr = waddr - {2'h0, wen ? cnt : cnt-1};
+  assign raddr = waddr - {2'h0, (wen ? cnt : cnt-1'b1)};
 
   always @(posedge CLK) begin
     if (wen) begin
       data[waddr] <= wdata;
-      waddr <= waddr+1;
+      waddr <= waddr+1'b1;
     end
   end
 

verilog/serializer.v

@@ -13,23 +13,23 @@ module serializer(
   reg [15:0] s1;
   reg [15:0] s2;
   reg [15:0] s3;
-  reg state = 0;
+  reg state = 1'b0;
 
-  reg [1:0] cnt = 0;
+  reg [1:0] cnt = 2'h0;
 
   always @(posedge CLK) begin
-    if (state == 0 && valid) begin
-      cnt <= 0;
+    if (state == 1'b0 && valid) begin
+      cnt <= 2'h0;
       // s1 <= I[1];
       // s2 <= I[2];
       // s3 <= I[3];
       s1 <= I1;
       s2 <= I2;
       s3 <= I3;
-      state <= 1;
+      state <= 1'b1;
     end else begin
-        cnt <= cnt + 1;
-        state <= cnt == 2 ? 0 : 1;
+        cnt <= cnt + 1'b1;
+        state <= cnt == 2'h2 ? 1'b0 : 1'b1;
     end
   end
 

verilog/uart.v

@@ -1,37 +1,33 @@
 module uart_tx(input CLK, input [7:0] data, input valid, output tx, output ready);
     reg [7:0] message;
-    reg [2:0] send_cnt;
-    reg [1:0] state = 0;
+    reg [2:0] send_cnt = 3'h0; //Was not initialized. 
+    reg [1:0] state = 2'h0;
     always @(posedge CLK) begin
         case (state)
-            0: 
+            2'h0: 
                 if (valid) begin
                     message <= data;
-                    tx <= 0;  // start bit
-                    state <= 1;
-                    send_cnt <= 7;
-                    ready <= 0;
+                    tx <= 1'b0;  // start bit
+                    state <= 2'h1;
+                    send_cnt <= 3'h7;
+                    ready <= 1'b0;
                 end else begin
-                    tx <= 1;
-                    state <= 0;
-                    ready <= 1;
+                    tx <= 1'b1;
+                    state <= 2'h0;
+                    ready <= 1'b1;
                 end
-            1:
+            2'h1:
                 begin
-                    ready <= 0;
+                    ready <= 1'b0;
                     tx <= message[send_cnt];
-                    send_cnt <= send_cnt - 1;
-                    if (send_cnt > 0) begin
-                        state <= 1;
-                    end else begin
-                        state <= 2;
-                    end
+                    send_cnt <= send_cnt - 1'b1;
+                    state <= (send_cnt > 0) ? 2'h1 : 2'h2;
                 end
-            2:
+            2'h2:
                 begin
-                    ready <= 0;
-                    tx <= 1; // end bit
-                    state <= 0;
+                    ready <= 1'b0;
+                    tx <= 1'b1; // end bit
+                    state <= 2'h0;
                 end
         endcase
         /* $display("valid=%d", valid); */