Add note about synchronous reset

leonardt · Oct 18, 2019 · dd43e5f · dd43e5f
1 parent 10430ef
commit dd43e5f
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/sdram/fsm.py b/sdram/fsm.py
@@ -50,6 +50,7 @@
 CMD_WRIT = "8'b10100xx1"
 
 
+# TODO: Add synchronous reset negedge
 class SDRAM(FSM):
     inputs = {
         "refresh_cnt": Bits[10],