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Merge pull request #1415 from selvintxavier/genp7_support
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bnxt_re/lib: Initial support for GenP7 adapters
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@rleon
rleon committed Dec 20, 2023
2 parents 9016f34 + d5d79c8 commit 331d5a0
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Showing 8 changed files with 262 additions and 24 deletions.
31 changes: 31 additions & 0 deletions kernel-headers/rdma/bnxt_re-abi.h
View file
Expand Up @@ -102,11 +102,16 @@ struct bnxt_re_cq_req {
__aligned_u64 cq_handle;
};

enum bnxt_re_cq_mask {
BNXT_RE_CQ_TOGGLE_PAGE_SUPPORT = 0x1,
};

struct bnxt_re_cq_resp {
__u32 cqid;
__u32 tail;
__u32 phase;
__u32 rsvd;
__aligned_u64 comp_mask;
};

struct bnxt_re_resize_cq_req {
Expand Down Expand Up @@ -143,6 +148,7 @@ enum bnxt_re_shpg_offt {
enum bnxt_re_objects {
BNXT_RE_OBJECT_ALLOC_PAGE = (1U << UVERBS_ID_NS_SHIFT),
BNXT_RE_OBJECT_NOTIFY_DRV,
BNXT_RE_OBJECT_GET_TOGGLE_MEM,
};

enum bnxt_re_alloc_page_type {
Expand Down Expand Up @@ -171,4 +177,29 @@ enum bnxt_re_alloc_page_methods {
enum bnxt_re_notify_drv_methods {
BNXT_RE_METHOD_NOTIFY_DRV = (1U << UVERBS_ID_NS_SHIFT),
};

/* Toggle mem */

enum bnxt_re_get_toggle_mem_type {
BNXT_RE_CQ_TOGGLE_MEM = 0,
BNXT_RE_SRQ_TOGGLE_MEM,
};

enum bnxt_re_var_toggle_mem_attrs {
BNXT_RE_TOGGLE_MEM_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
BNXT_RE_TOGGLE_MEM_TYPE,
BNXT_RE_TOGGLE_MEM_RES_ID,
BNXT_RE_TOGGLE_MEM_MMAP_PAGE,
BNXT_RE_TOGGLE_MEM_MMAP_OFFSET,
BNXT_RE_TOGGLE_MEM_MMAP_LENGTH,
};

enum bnxt_re_toggle_mem_attrs {
BNXT_RE_RELEASE_TOGGLE_MEM_HANDLE = (1U << UVERBS_ID_NS_SHIFT),
};

enum bnxt_re_toggle_mem_methods {
BNXT_RE_METHOD_GET_TOGGLE_MEM = (1U << UVERBS_ID_NS_SHIFT),
BNXT_RE_METHOD_RELEASE_TOGGLE_MEM,
};
#endif /* __BNXT_RE_UVERBS_ABI_H__*/
33 changes: 31 additions & 2 deletions providers/bnxt_re/bnxt_re-abi.h
View file
Expand Up @@ -145,7 +145,7 @@ enum bnxt_re_db_que_type {
};

enum bnxt_re_db_mask {
BNXT_RE_DB_INDX_MASK = 0xFFFFFUL,
BNXT_RE_DB_INDX_MASK = 0xFFFFFFUL,
BNXT_RE_DB_PILO_MASK = 0x0FFUL,
BNXT_RE_DB_PILO_SHIFT = 0x18,
BNXT_RE_DB_QID_MASK = 0xFFFFFUL,
Expand All @@ -154,7 +154,8 @@ enum bnxt_re_db_mask {
BNXT_RE_DB_TYP_MASK = 0x0FUL,
BNXT_RE_DB_TYP_SHIFT = 0x1C,
BNXT_RE_DB_VALID_SHIFT = 0x1A,
BNXT_RE_DB_EPOCH_SHIFT = 0x18
BNXT_RE_DB_EPOCH_SHIFT = 0x18,
BNXT_RE_DB_TOGGLE_SHIFT = 0x19,
};

enum bnxt_re_psns_mask {
Expand All @@ -166,10 +167,21 @@ enum bnxt_re_psns_mask {
BNXT_RE_PSNS_FLAGS_SHIFT = 0x18
};

enum bnxt_re_msns_mask {
BNXT_RE_SQ_MSN_SEARCH_START_PSN_MASK = 0xFFFFFFUL,
BNXT_RE_SQ_MSN_SEARCH_START_PSN_SHIFT = 0,
BNXT_RE_SQ_MSN_SEARCH_NEXT_PSN_MASK = 0xFFFFFF000000ULL,
BNXT_RE_SQ_MSN_SEARCH_NEXT_PSN_SHIFT = 0x18,
BNXT_RE_SQ_MSN_SEARCH_START_IDX_MASK = 0xFFFF000000000000ULL,
BNXT_RE_SQ_MSN_SEARCH_START_IDX_SHIFT = 0x30
};

enum bnxt_re_bcqe_mask {
BNXT_RE_BCQE_PH_MASK = 0x01,
BNXT_RE_BCQE_TYPE_MASK = 0x0F,
BNXT_RE_BCQE_TYPE_SHIFT = 0x01,
BNXT_RE_BCQE_RESIZE_TOG_MASK = 0x03,
BNXT_RE_BCQE_RESIZE_TOG_SHIFT = 0x05,
BNXT_RE_BCQE_STATUS_MASK = 0xFF,
BNXT_RE_BCQE_STATUS_SHIFT = 0x08,
BNXT_RE_BCQE_FLAGS_MASK = 0xFFFFU,
Expand Down Expand Up @@ -215,6 +227,18 @@ enum {
BNXT_RE_COMP_MASK_UCNTX_POW2_DISABLED = 0x04,
};

enum bnxt_re_que_flags_mask {
BNXT_RE_FLAG_EPOCH_TAIL_SHIFT = 0x0UL,
BNXT_RE_FLAG_EPOCH_HEAD_SHIFT = 0x1UL,
BNXT_RE_FLAG_EPOCH_TAIL_MASK = 0x1UL,
BNXT_RE_FLAG_EPOCH_HEAD_MASK = 0x2UL,
};

enum bnxt_re_db_epoch_flag_shift {
BNXT_RE_DB_EPOCH_TAIL_SHIFT = BNXT_RE_DB_EPOCH_SHIFT,
BNXT_RE_DB_EPOCH_HEAD_SHIFT = (BNXT_RE_DB_EPOCH_SHIFT - 1)
};

enum bnxt_re_modes {
BNXT_RE_WQE_MODE_STATIC = 0x00,
BNXT_RE_WQE_MODE_VARIABLE = 0x01
Expand Down Expand Up @@ -286,6 +310,11 @@ struct bnxt_re_psns_ext {
__u32 rsvd1;
};

/* sq_msn_search (size:64b/8B) */
struct bnxt_re_msns {
__le64 start_idx_next_psn_start_psn;
};

struct bnxt_re_sge {
__le64 pa;
__le32 lkey;
Expand Down
38 changes: 28 additions & 10 deletions providers/bnxt_re/db.c
View file
Expand Up @@ -106,43 +106,52 @@ static void bnxt_re_ring_db(struct bnxt_re_dpi *dpi,
}

static void bnxt_re_init_db_hdr(struct bnxt_re_db_hdr *hdr, uint32_t indx,
uint32_t qid, uint32_t typ)
uint32_t qid, uint32_t toggle, uint32_t typ)
{
hdr->indx = htole32(indx & BNXT_RE_DB_INDX_MASK);
hdr->indx = htole32(indx | toggle << BNXT_RE_DB_TOGGLE_SHIFT);
hdr->typ_qid = htole32(qid & BNXT_RE_DB_QID_MASK);
hdr->typ_qid |= htole32(((typ & BNXT_RE_DB_TYP_MASK) <<
BNXT_RE_DB_TYP_SHIFT));
BNXT_RE_DB_TYP_SHIFT) | (0x1UL << BNXT_RE_DB_VALID_SHIFT));
}

void bnxt_re_ring_rq_db(struct bnxt_re_qp *qp)
{
struct bnxt_re_db_hdr hdr;
uint32_t epoch;
uint32_t tail;

bnxt_re_do_pacing(qp->cntx, &qp->rand);
tail = *qp->jrqq->hwque->dbtail;
bnxt_re_init_db_hdr(&hdr, tail, qp->qpid, BNXT_RE_QUE_TYPE_RQ);
epoch = (qp->jrqq->hwque->flags & BNXT_RE_FLAG_EPOCH_TAIL_MASK) <<
BNXT_RE_DB_EPOCH_TAIL_SHIFT;
bnxt_re_init_db_hdr(&hdr, tail | epoch,
qp->qpid, 0, BNXT_RE_QUE_TYPE_RQ);
bnxt_re_ring_db(qp->udpi, &hdr);
}

void bnxt_re_ring_sq_db(struct bnxt_re_qp *qp)
{
struct bnxt_re_db_hdr hdr;
uint32_t epoch;
uint32_t tail;

bnxt_re_do_pacing(qp->cntx, &qp->rand);
tail = *qp->jsqq->hwque->dbtail;
bnxt_re_init_db_hdr(&hdr, tail, qp->qpid, BNXT_RE_QUE_TYPE_SQ);
epoch = (qp->jsqq->hwque->flags & BNXT_RE_FLAG_EPOCH_TAIL_MASK) <<
BNXT_RE_DB_EPOCH_TAIL_SHIFT;
bnxt_re_init_db_hdr(&hdr, tail | epoch, qp->qpid, 0, BNXT_RE_QUE_TYPE_SQ);
bnxt_re_ring_db(qp->udpi, &hdr);
}

void bnxt_re_ring_srq_db(struct bnxt_re_srq *srq)
{
struct bnxt_re_db_hdr hdr;
uint32_t epoch;

bnxt_re_do_pacing(srq->cntx, &srq->rand);
bnxt_re_init_db_hdr(&hdr, srq->srqq->tail, srq->srqid,
BNXT_RE_QUE_TYPE_SRQ);
epoch = (srq->srqq->flags & BNXT_RE_FLAG_EPOCH_TAIL_MASK) <<
BNXT_RE_DB_EPOCH_TAIL_SHIFT;
bnxt_re_init_db_hdr(&hdr, srq->srqq->tail | epoch, srq->srqid, 0, BNXT_RE_QUE_TYPE_SRQ);
bnxt_re_ring_db(srq->udpi, &hdr);
}

Expand All @@ -151,26 +160,35 @@ void bnxt_re_ring_srq_arm(struct bnxt_re_srq *srq)
struct bnxt_re_db_hdr hdr;

bnxt_re_do_pacing(srq->cntx, &srq->rand);
bnxt_re_init_db_hdr(&hdr, srq->cap.srq_limit, srq->srqid,
bnxt_re_init_db_hdr(&hdr, srq->cap.srq_limit, srq->srqid, 0,
BNXT_RE_QUE_TYPE_SRQ_ARM);
bnxt_re_ring_db(srq->udpi, &hdr);
}

void bnxt_re_ring_cq_db(struct bnxt_re_cq *cq)
{
struct bnxt_re_db_hdr hdr;
uint32_t epoch;

bnxt_re_do_pacing(cq->cntx, &cq->rand);
bnxt_re_init_db_hdr(&hdr, cq->cqq.head, cq->cqid, BNXT_RE_QUE_TYPE_CQ);
epoch = (cq->cqq.flags & BNXT_RE_FLAG_EPOCH_HEAD_MASK) << BNXT_RE_DB_EPOCH_HEAD_SHIFT;
bnxt_re_init_db_hdr(&hdr, cq->cqq.head | epoch, cq->cqid, 0, BNXT_RE_QUE_TYPE_CQ);
bnxt_re_ring_db(cq->udpi, &hdr);
}

void bnxt_re_ring_cq_arm_db(struct bnxt_re_cq *cq, uint8_t aflag)
{
uint32_t epoch, toggle = 0;
struct bnxt_re_db_hdr hdr;
uint32_t *pgptr;

pgptr = (uint32_t *)cq->toggle_map;
if (pgptr)
toggle = *pgptr;

bnxt_re_do_pacing(cq->cntx, &cq->rand);
bnxt_re_init_db_hdr(&hdr, cq->cqq.head, cq->cqid, aflag);
epoch = (cq->cqq.flags & BNXT_RE_FLAG_EPOCH_HEAD_MASK) << BNXT_RE_DB_EPOCH_HEAD_SHIFT;
bnxt_re_init_db_hdr(&hdr, cq->cqq.head | epoch, cq->cqid, toggle, aflag);
bnxt_re_ring_db(cq->udpi, &hdr);
}

Expand Down
13 changes: 12 additions & 1 deletion providers/bnxt_re/main.c
View file
Expand Up @@ -121,13 +121,24 @@ static const struct verbs_context_ops bnxt_re_cntx_ops = {
.free_context = bnxt_re_free_context,
};

static inline bool bnxt_re_is_chip_gen_p7(struct bnxt_re_chip_ctx *cctx)
{
return (cctx->chip_num == CHIP_NUM_58818 ||
cctx->chip_num == CHIP_NUM_57608);
}

static bool bnxt_re_is_chip_gen_p5(struct bnxt_re_chip_ctx *cctx)
{
return (cctx->chip_num == CHIP_NUM_57508 ||
cctx->chip_num == CHIP_NUM_57504 ||
cctx->chip_num == CHIP_NUM_57502);
}

static inline bool bnxt_re_is_chip_gen_p5_p7(struct bnxt_re_chip_ctx *cctx)
{
return bnxt_re_is_chip_gen_p5(cctx) || bnxt_re_is_chip_gen_p7(cctx);
}

static int bnxt_re_alloc_map_dbr_page(struct ibv_context *ibvctx)
{
struct bnxt_re_context *cntx = to_bnxt_re_context(ibvctx);
Expand Down Expand Up @@ -199,7 +210,7 @@ static struct verbs_context *bnxt_re_alloc_context(struct ibv_device *vdev,
cntx->cctx.chip_metal = (resp.chip_id0 >>
BNXT_RE_CHIP_ID0_CHIP_MET_SFT) &
0xFF;
cntx->cctx.gen_p5 = bnxt_re_is_chip_gen_p5(&cntx->cctx);
cntx->cctx.gen_p5_p7 = bnxt_re_is_chip_gen_p5_p7(&cntx->cctx);
}

if (resp.comp_mask & BNXT_RE_UCNTX_CMASK_HAVE_MODE)
Expand Down
16 changes: 15 additions & 1 deletion providers/bnxt_re/main.h
View file
Expand Up @@ -62,6 +62,9 @@
#define CHIP_NUM_57508 0x1750
#define CHIP_NUM_57504 0x1751
#define CHIP_NUM_57502 0x1752
#define CHIP_NUM_58818 0xd818
#define CHIP_NUM_57608 0x1760

#define BNXT_RE_MAX_DO_PACING 0xFFFF
#define BNXT_NSEC_PER_SEC 1000000000UL
#define BNXT_RE_PAGE_MASK(pg_size) (~((__u64)(pg_size) - 1))
Expand All @@ -70,7 +73,8 @@ struct bnxt_re_chip_ctx {
__u16 chip_num;
__u8 chip_rev;
__u8 chip_metal;
__u8 gen_p5;
__u8 gen_p5_p7;
__u8 gen_p7;
};

struct bnxt_re_dpi {
Expand Down Expand Up @@ -98,6 +102,9 @@ struct bnxt_re_cq {
uint32_t cqe_size;
uint8_t phase;
struct xorshift32_state rand;
uint32_t mem_handle;
void *toggle_map;
uint32_t toggle_size;
};

struct bnxt_re_push_buffer {
Expand Down Expand Up @@ -250,6 +257,8 @@ struct bnxt_re_mmap_info {
__u32 dpi;
__u64 alloc_offset;
__u32 alloc_size;
__u32 pg_offset;
__u32 res_id;
};

/* DB ring functions used internally*/
Expand Down Expand Up @@ -278,6 +287,9 @@ int bnxt_re_alloc_page(struct ibv_context *ibvctx,
struct bnxt_re_mmap_info *minfo,
uint32_t *page_handle);
int bnxt_re_notify_drv(struct ibv_context *ibvctx);
int bnxt_re_get_toggle_mem(struct ibv_context *ibvctx,
struct bnxt_re_mmap_info *minfo,
uint32_t *page_handle);

/* pointer conversion functions*/
static inline struct bnxt_re_dev *to_bnxt_re_dev(struct ibv_device *ibvdev)
Expand Down Expand Up @@ -597,4 +609,6 @@ static inline void bnxt_re_sub_sec_busy_wait(uint32_t nsec)
break;
}
}

#define BNXT_RE_HW_RETX(a) ((a)->comp_mask & BNXT_RE_COMP_MASK_UCNTX_HW_RETX_ENABLED)
#endif
15 changes: 13 additions & 2 deletions providers/bnxt_re/memory.h
View file
Expand Up @@ -44,12 +44,15 @@

struct bnxt_re_queue {
void *va;
uint32_t flags;
uint32_t *dbtail;
uint32_t bytes; /* for munmap */
uint32_t depth; /* no. of entries */
uint32_t head;
uint32_t tail;
uint32_t stride;
void *pad; /* to hold the padding area */
uint32_t pad_stride_log2;
/* Represents the difference between the real queue depth allocated in
* HW and the user requested queue depth and is used to correctly flag
* queue full condition based on user supplied queue depth.
Expand All @@ -61,6 +64,8 @@ struct bnxt_re_queue {
uint32_t esize;
uint32_t max_slots;
pthread_spinlock_t qlock;
uint32_t msn;
uint32_t msn_tbl_sz;
};

int bnxt_re_alloc_aligned(struct bnxt_re_queue *que, uint32_t pg_size);
Expand Down Expand Up @@ -101,15 +106,21 @@ static inline uint32_t bnxt_re_is_que_empty(struct bnxt_re_queue *que)
static inline void bnxt_re_incr_tail(struct bnxt_re_queue *que, uint8_t cnt)
{
que->tail += cnt;
if (que->tail >= que->depth)
if (que->tail >= que->depth) {
que->tail %= que->depth;
/* Rolled over, Toggle Tail bit in epoch flags */
que->flags ^= 1UL << BNXT_RE_FLAG_EPOCH_TAIL_SHIFT;
}
}

static inline void bnxt_re_incr_head(struct bnxt_re_queue *que, uint8_t cnt)
{
que->head += cnt;
if (que->head >= que->depth)
if (que->head >= que->depth) {
que->head %= que->depth;
/* Rolled over, Toggle HEAD bit in epoch flags */
que->flags ^= 1UL << BNXT_RE_FLAG_EPOCH_HEAD_SHIFT;
}
}

#endif

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