tests: Add DrDestDevxTirAction test

Add a test that creates devx TIR, dest TIR action on the RX,
and sends raw traffic.

Signed-off-by: Shachar Kagan <skagan@nvidia.com>
Signed-off-by: Edward Srouji <edwards@nvidia.com>

tests/mlx5_prm_structs.py

@@ -37,6 +37,7 @@ class DevxOps:
     MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939
     MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a
     MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b
+    MLX5_CMD_OP_CREATE_TIR = 0x900
 
 
 # Common
@@ -1337,3 +1338,71 @@ class QueryFlowCounterOut(Packet):
         StrFixedLenField('reserved2', None, length=8),
         PacketField('flow_statistics', TrafficCounter(), TrafficCounter),
     ]
+
+
+class RxHashFieldSelect(Packet):
+    fields_desc = [
+        BitField('l3_prot_type', 0, 1),
+        BitField('l4_prot_type', 0, 1),
+        BitField('selected_fields', 0, 30),
+    ]
+
+
+class Tirc(Packet):
+    fields_desc = [
+        StrFixedLenField('reserved1', None, length=4),
+        BitField('disp_type', 0, 4),
+        BitField('tls_en', 0, 1),
+        BitField('nvmeotcp_zerocopy_en', 0, 1),
+        BitField('nvmeotcp_crc_en', 0, 1),
+        BitField('reserved2', 0, 25),
+        StrFixedLenField('reserved3', None, length=8),
+        BitField('reserved4', 0, 4),
+        BitField('lro_timeout_period_usecs', 0, 16),
+        BitField('lro_enable_mask', 0, 4),
+        ByteField('lro_max_msg_sz', 0),
+        ByteField('reserved5', 0),
+        BitField('afu_id', 0, 24),
+        BitField('inline_rqn_vhca_id_valid', 0, 1),
+        BitField('reserved6', 0, 15),
+        ShortField('inline_rqn_vhca_id', 0),
+        BitField('reserved7', 0, 5),
+        BitField('inline_q_type', 0, 3),
+        BitField('inline_rqn', 0, 24),
+        BitField('rx_hash_symmetric', 0, 1),
+        BitField('reserved8', 0, 1),
+        BitField('tunneled_offload_en', 0, 1),
+        BitField('reserved9', 0, 5),
+        BitField('indirect_table', 0, 24),
+        BitField('rx_hash_fn', 0, 4),
+        BitField('reserved10', 0, 2),
+        BitField('self_lb_en', 0, 2),
+        BitField('transport_domain', 0, 24),
+        FieldListField('rx_hash_toeplitz_key', [0 for x in range(10)], IntField('', 0), count_from=lambda pkt:10),
+        PacketField('rx_hash_field_selector_outer', RxHashFieldSelect(), RxHashFieldSelect),
+        PacketField('rx_hash_field_selector_inner', RxHashFieldSelect(), RxHashFieldSelect),
+        IntField('nvmeotcp_tag_buffer_table_id', 0),
+        StrFixedLenField('reserved11', None, length=148),
+    ]
+
+
+class CreateTirIn(Packet):
+    fields_desc = [
+        ShortField('opcode', DevxOps.MLX5_CMD_OP_CREATE_TIR),
+        ShortField('uid', 0),
+        ShortField('reserved1', 0),
+        ShortField('op_mod', 0),
+        StrFixedLenField('reserved2', None, length=24),
+        PacketField('tir_context', Tirc(), Tirc),
+    ]
+
+
+class CreateTirOut(Packet):
+    fields_desc = [
+        ByteField('status', 0),
+        BitField('icm_address_63_40', 0, 24),
+        IntField('syndrome', 0),
+        ByteField('icm_address_39_32', 0),
+        BitField('tirn', 0, 24),
+        IntField('icm_address_31_0', 0),
+    ]

tests/test_mlx5_dr.py

@@ -12,7 +12,7 @@
 from pyverbs.providers.mlx5.dr_action import DrActionQp, DrActionModify, \
     DrActionFlowCounter, DrActionDrop, DrActionTag, DrActionDestTable, \
     DrActionPopVLan, DrActionPushVLan, DrActionDestAttr, DrActionDestArray, \
-    DrActionDefMiss, DrActionVPort, DrActionIBPort
+    DrActionDefMiss, DrActionVPort, DrActionIBPort, DrActionDestTir
 from pyverbs.providers.mlx5.mlx5dv import Mlx5DevxObj, Mlx5Context, Mlx5DVContextAttr
 from tests.utils import skip_unsupported, requires_root_on_eth, requires_eswitch_on, \
     PacketConsts
@@ -25,7 +25,8 @@
 from pyverbs.providers.mlx5.dr_rule import DrRule
 import pyverbs.providers.mlx5.mlx5_enums as dve
 
-from pyverbs.cq import CqInitAttrEx, CQEX
+from pyverbs.cq import CqInitAttrEx, CQEX, CQ
+from pyverbs.wq import WQInitAttr, WQ, WQAttr
 from tests.base import RawResources
 import pyverbs.enums as e
 import tests.utils as u
@@ -95,6 +96,28 @@ def create_cq(self):
             raise ex
 
 
+class Mlx5DrTirResources(Mlx5DrResources):
+    def __init__(self, dev_name, ib_port, gid_index=0, wc_flags=0, msg_size=1024,
+                 qp_count=1, server=False):
+        self.server = server
+        super().__init__(dev_name=dev_name, ib_port=ib_port, gid_index=gid_index,
+                         wc_flags=wc_flags, msg_size=msg_size, qp_count=qp_count)
+
+    def create_cq(self):
+        self.cq = CQ(self.ctx, cqe=self.num_msgs)
+
+    @requires_root_on_eth()
+    def create_qps(self):
+        if not self.server:
+            super().create_qps()
+        else:
+            from tests.mlx5_prm_structs import Tirc, CreateTirIn, CreateTirOut
+            self.qps = [WQ(self.ctx, WQInitAttr(wq_pd=self.pd, wq_cq=self.cq))]
+            self.qps[0].modify(WQAttr(attr_mask=e.IBV_WQ_ATTR_STATE, wq_state=e.IBV_WQS_RDY))
+            tir_ctx = Tirc(inline_rqn=self.qps[0].wqn)
+            self.tir = Mlx5DevxObj(self.ctx, CreateTirIn(tir_context=tir_ctx), len(CreateTirOut()))
+
+
 class Mlx5DrTest(Mlx5RDMATestCase):
     def setUp(self):
         super().setUp()
@@ -494,6 +517,15 @@ def test_tx_def_miss_action(self):
         self.rules.append(DrRule(matcher_tx2, value_param, [tx_drop_action]))
         u.raw_traffic(self.client, self.server, self.iters)
 
+    @skip_unsupported
+    def test_dest_tir(self):
+        self.client = Mlx5DrTirResources(**self.dev_info)
+        self.server = Mlx5DrTirResources(**self.dev_info, server=True)
+        tir_action = DrActionDestTir(self.server.tir)
+        smac_value = struct.pack('!6s', bytes.fromhex(PacketConsts.SRC_MAC.replace(':', '')))
+        self.create_rx_recv_rules(smac_value, [tir_action])
+        u.raw_traffic(self.client, self.server, self.iters)
+
 
 class Mlx5DrDumpTest(PyverbsAPITestCase):
     def setUp(self):

tests/utils.py

@@ -21,7 +21,7 @@
 from tests.base import XRCResources, DCT_KEY
 from tests.efa_base import SRDResources
 from pyverbs.wr import SGE, SendWR, RecvWR
-from pyverbs.qp import QPCap, QPInitAttr, QPInitAttrEx, QPAttr, QPEx
+from pyverbs.qp import QPCap, QPInitAttr, QPInitAttrEx, QPAttr, QPEx, QP
 from tests.mlx5_base import Mlx5DcResources, Mlx5DcStreamsRes
 from pyverbs.base import PyverbsRDMAErrno
 from pyverbs.cq import PollCqAttr, CQEX
@@ -405,7 +405,7 @@ def get_recv_wr(agr_obj):
     :return: recv wr
     """
     qp_type = agr_obj.rqp_lst[0].qp_type if isinstance(agr_obj, XRCResources) \
-                else agr_obj.qp.qp_type
+        else agr_obj.qp.qp_type if isinstance(agr_obj.qp, QP) else None
     mr = agr_obj.mr
     length = agr_obj.msg_size + GRH_SIZE if qp_type == e.IBV_QPT_UD \
              else agr_obj.msg_size