mlx5: Provide reg C0 value for matching egress traffic

When provided the value can be used to match egress traffic from the local vport in the FDB. Signed-off-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Yishai Hadas <yishaih@nvidia.com>
linux-rdma · Dec 14, 2023 · c63abc0 · c63abc0
1 parent 98dd40b
commit c63abc0
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Showing 5 changed files with 13 additions and 0 deletions.
diff --git a/providers/mlx5/man/mlx5dv_query_device.3 b/providers/mlx5/man/mlx5dv_query_device.3
@@ -64,6 +64,7 @@ size_t max_wr_memcpy_length; /* max length that is supported by the DMA memcpy W
 struct mlx5dv_crypto_caps crypto_caps;
 uint64_t max_dc_rd_atom; /* Maximum number of outstanding RDMA read/atomic per DC QP as a requester */
 uint64_t max_dc_init_rd_atom; /* Maximum number of outstanding RDMA read/atomic per DC QP as a responder */
+struct mlx5dv_reg reg_c0; /* value and mask to match local vport egress traffic in FDB */
 .in -8
 };
 
@@ -105,6 +106,7 @@ MLX5DV_CONTEXT_MASK_DCI_STREAMS         = 1 << 11,
 MLX5DV_CONTEXT_MASK_WR_MEMCPY_LENGTH    = 1 << 12,
 MLX5DV_CONTEXT_MASK_CRYPTO_OFFLOAD      = 1 << 13,
 MLX5DV_CONTEXT_MASK_MAX_DC_RD_ATOM      = 1 << 14,
+MLX5DV_CONTEXT_MASK_REG_C0              = 1 << 15,
 .in -8
 };
 

diff --git a/providers/mlx5/mlx5.c b/providers/mlx5/mlx5.c
@@ -971,6 +971,13 @@ static int _mlx5dv_query_device(struct ibv_context *ctx_in,
 		comp_mask_out |= MLX5DV_CONTEXT_MASK_MAX_DC_RD_ATOM;
 	}
 
+	if (attrs_out->comp_mask & MLX5DV_CONTEXT_MASK_REG_C0) {
+		if (mctx->reg_c0.mask) {
+			attrs_out->reg_c0 = mctx->reg_c0;
+			comp_mask_out |= MLX5DV_CONTEXT_MASK_REG_C0;
+		}
+	}
+
 	attrs_out->comp_mask = comp_mask_out;
 
 	return 0;

diff --git a/providers/mlx5/mlx5.h b/providers/mlx5/mlx5.h
@@ -422,6 +422,7 @@ struct mlx5_context {
 	pthread_mutex_t			crypto_login_mutex;
 	uint64_t			max_dc_rd_atom;
 	uint64_t			max_dc_init_rd_atom;
+	struct mlx5dv_reg		reg_c0;
 };
 
 struct mlx5_hugetlb_mem {

diff --git a/providers/mlx5/mlx5dv.h b/providers/mlx5/mlx5dv.h
@@ -87,6 +87,7 @@ enum mlx5dv_context_comp_mask {
 	MLX5DV_CONTEXT_MASK_WR_MEMCPY_LENGTH	= 1 << 12,
 	MLX5DV_CONTEXT_MASK_CRYPTO_OFFLOAD	= 1 << 13,
 	MLX5DV_CONTEXT_MASK_MAX_DC_RD_ATOM	= 1 << 14,
+	MLX5DV_CONTEXT_MASK_REG_C0		= 1 << 15,
 };
 
 struct mlx5dv_cqe_comp_caps {
@@ -235,6 +236,7 @@ struct mlx5dv_context {
 	struct mlx5dv_crypto_caps crypto_caps;
 	uint64_t max_dc_rd_atom;
 	uint64_t max_dc_init_rd_atom;
+	struct mlx5dv_reg reg_c0;
 };
 
 enum mlx5dv_context_flags {

diff --git a/providers/mlx5/verbs.c b/providers/mlx5/verbs.c
@@ -4091,6 +4091,7 @@ void mlx5_query_device_ctx(struct mlx5_context *mctx)
 		resp.dci_streams_caps.max_log_num_concurent;
 	mctx->dci_streams_caps.max_log_num_errored =
 		resp.dci_streams_caps.max_log_num_errored;
+	mctx->reg_c0 = resp.reg_c0;
 
 	if (resp.flags & MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP)
 		mctx->vendor_cap_flags |= MLX5_VENDOR_CAP_FLAGS_CQE_128B_COMP;