libhns: Add support for direct wqe #1088
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To commit 0045e0d3f42e ("RDMA/hns: Support direct wqe of userspace").
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
The current write wqe mechanism is to write to DDR first, and then notify
the hardware through doorbell to read the data. Direct wqe is a mechanism
to fill wqe directly into the hardware. In the case of light load, the wqe
will be filled into pcie bar space of the hardware, this will reduce one
memory access operation and therefore reduce the latency. SIMD instructions
allows cpu to write the 512 bits at one time to device memory, thus it can
be used for posting direct wqe.
The process of post send of HIP08/09:
+-----------+
| post send |
+-----+-----+
|
+-----+-----+
| write WQE |
+-----+-----+
|
| udma_to_device_barrier()
|
+-----+-----+ Y +-----------+ N
| HIP09 ? +------+ multi WR ?+-------------+
+-----+-----+ +-----+-----+ |
| N | Y |
+-----+-----+ +-----+-----+ +--------+--------+
| ring DB | | ring DB | |direct WQE (ST4) |
+-----------+ +-----------+ +-----------------+
Signed-off-by: Yixing Liu <liuyixing1@huawei.com>
Signed-off-by: Lang Cheng <chenglang@huawei.com>
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
|
Gentle ping... Hi, @rleon Whether this PR is normal, its kernel part has been merged, thanks. |
rleon
reviewed
Dec 18, 2021
| _mmio_memcpy_x64_64b(dest, src); | ||
| bytecnt -= sizeof(uint64x2x4_t); | ||
| src += sizeof(uint64x2x4_t); | ||
| } while (bytecnt > 0); |
There was a problem hiding this comment.
You should be very careful here, bytecnt is size_t => unsigned.
Sorry for the delay |
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Direct wqe is a mechanism to fill wqe directly into the hardware. In the
case of light load, the wqe will be filled into pcie bar space of the
hardware, this will reduce one memory access operation and therefore reduce
the latency.
The kernel parts is named "RDMA/hns: Support direct WQE of userspace".
Changes since v2:
Changes since v1: