Barriers #95
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Barriers #95
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Please replace patch 1 with the version I sent to the list, otherwise looks fine. Thanks for looking at this. |
For x86 the serialization within the spin lock is enough to strongly order WC and other memory types. Add a new barrier named 'mmio_wc_spinlock' to optimize that. The mmio_wc_spinunlock barrier was added as well, it may be optimized in some further step based on some required justification. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Reviewed-by: Yishai Hadas <yishaih@mellanox.com>
This patch optimize current implementation as follow: - Drop the leading barrier which affects non X86 ARCH(s) till making further optimization to prevent performance degradation. - In ARCH(s) that spinlock() serves also as SFENCE prevent an another explicit SFENCE. (e.g. X86). Signed-off-by: Yishai Hadas <yishaih@mellanox.com>
In ARCH(s) that spinlock() serves also as SFENCE prevent an another explicit SFENCE. (e.g. X86). To prevent an extra 'if' to know whether lock is really taken and it's not a single threaded application encapsulates the mlx5_single_threaded flag as part of bf->need_lock. Signed-off-by: Yishai Hadas <yishaih@mellanox.com>
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This series comes to optimize both mlx4 and mlx5 as some follow-up of previous
barrier series that was already merged.