Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Add notifier for PLL0 clock and set it 1.5GHz on #848

Closed
wants to merge 2 commits into from
Closed

Add notifier for PLL0 clock and set it 1.5GHz on #848

wants to merge 2 commits into from

Commits on Apr 10, 2024

  1. clk: starfive: jh7110-sys: Add notifier for PLL clock 

    Add notifier function for PLL clock. In the function, the cpu_root clock
should be operated by saving its current parent and setting a new safe
parent (osc clock) before setting the PLL clock rate. After setting PLL
rate, it should be switched back to the original parent clock.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
    @SFxingyuwu
    SFxingyuwu authored and Björn Töpel committed Apr 10, 2024
    Configuration menu
    Copy the full SHA
    3bd300f View commit details
    Browse the repository at this point in the history

  2. riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by sett… 

    …ing PLL0 rate to 1.5GHz

CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz.
But now PLL0 rate is 1GHz and the cpu frequency loads become
333/500/500/1000MHz in fact.

So PLL0 rate should be default set to 1.5GHz and set the
cpu_core rate to 500MHz in safe.

Fixes: e2c510d ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC")
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
    @SFxingyuwu
    SFxingyuwu authored and Björn Töpel committed Apr 10, 2024
    Configuration menu
    Copy the full SHA
    e0407b8 View commit details
    Browse the repository at this point in the history