Support multicore CPU configuration

[mithro]

We should extend this repository to support multicore configurations. To support this, there is a bunch of work that would need to be done, specially to VexRISCV.

@SpinalHDL / @Dolu1990 - Could you enumerate what would be needed?

[Dolu1990]

Long answer there : SpinalHDL/VexRiscv#85 (comment)
But to resume :

• Coherent D$
• Coherent interconnect
• But first i would like to boost the I$ D$ memory bus data width first. Would that be fine in litex ?

[enjoy-digital]

@Dolu1990: thanks. Yes increasing the memory bus data width will be possible (and we'll probably work on that soon since this is also useful for Rocket that is currently down-converted to 32-bit (just to have a first working version) but should be 64-bit).

[enjoy-digital]

#47 and #126 are duplicate, let's continue the discussion in #126.