Merge pull request #69 from motec-research/no_mmap

SDRPHY: support flash=None
litex-hub · Feb 1, 2024 · 3a0651d · 3a0651d
2 parents a18df94 + fa4f662
commit 3a0651d
Showing 1 changed file with 12 additions and 8 deletions.
diff --git a/litespi/phy/generic_sdr.py b/litespi/phy/generic_sdr.py
@@ -82,16 +82,20 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
             bus_width = len(pads.dq)
         assert bus_width in [1, 2, 4, 8]
 
-        # Check if number of pads matches configured mode.
-        assert flash.check_bus_width(bus_width)
+        if flash:
+            # Check if number of pads matches configured mode.
+            assert flash.check_bus_width(bus_width)
 
-        self.addr_bits  = addr_bits  = flash.addr_bits
-        self.cmd_width  = cmd_width  = flash.cmd_width
-        self.addr_width = addr_width = flash.addr_width
-        self.data_width = data_width = flash.bus_width
-        self.ddr        = ddr        = flash.ddr
+            self.addr_bits  = addr_bits  = flash.addr_bits
+            self.cmd_width  = cmd_width  = flash.cmd_width
+            self.addr_width = addr_width = flash.addr_width
+            self.data_width = data_width = flash.bus_width
+            self.ddr        = ddr        = flash.ddr
 
-        self.command = command = flash.read_opcode.code
+            self.command = command = flash.read_opcode.code
+        else:
+            # master only
+            self.ddr        = ddr        = False
 
         # Clock Generator.
         self.submodules.clkgen = clkgen = LiteSPIClkGen(pads, device, with_ddr=ddr)