Merge pull request #134 from Disasm/fix-orangecrab

Fix FPGA reset logic for orangecrab target
litex-hub · Dec 21, 2020 · 36b7fb1 · 36b7fb1
2 parents e1f9fd1 + f6a106c
commit 36b7fb1
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py
@@ -69,7 +69,7 @@ def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
         reset_timer = WaitTimer(sys_clk_freq)
         self.submodules += reset_timer
         self.comb += reset_timer.wait.eq(~rst_n)
-        self.comb += platform.request("rst_n").eq(reset_timer.done)
+        self.comb += platform.request("rst_n").eq(~reset_timer.done)
 
 
 class _CRGSDRAM(Module):