icebreaker/fomu: Fix SPRAM split.

litex-hub · Sep 30, 2021 · 82653cf · 82653cf
1 parent 5addd7f
commit 82653cf
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Showing 3 changed files with 21 additions and 6 deletions.
diff --git a/litex_boards/targets/1bitsquared_icebreaker.py b/litex_boards/targets/1bitsquared_icebreaker.py
@@ -92,10 +92,15 @@ def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_led_chaser=Tr
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.submodules.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
+        self.bus.add_region("sram", SoCRegion(
+                origin = self.bus.regions["psram"].origin + 0*kB,
+                size   = 64*kB,
+                linker = True)
+        )
         if not self.integrated_main_ram_size:
             self.bus.add_region("main_ram", SoCRegion(
-                origin = self.bus.regions["sram"].origin + 64*kB,
+                origin = self.bus.regions["psram"].origin + 64*kB,
                 size   = 64*kB,
                 linker = True)
             )

diff --git a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
@@ -87,10 +87,15 @@ def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), revision="v1", **k
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.submodules.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
+        self.bus.add_region("sram", SoCRegion(
+                origin = self.bus.regions["psram"].origin + 0*kB,
+                size   = 64*kB,
+                linker = True)
+        )
         if not self.integrated_main_ram_size:
             self.bus.add_region("main_ram", SoCRegion(
-                origin = self.bus.regions["sram"].origin + 64*kB,
+                origin = self.bus.regions["psram"].origin + 64*kB,
                 size   = 64*kB,
                 linker = True)
             )

diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py
@@ -97,10 +97,15 @@ def __init__(self, bios_flash_offset, spi_flash_module="AT25SF161", sys_clk_freq
 
         # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
         self.submodules.spram = Up5kSPRAM(size=128*kB)
-        self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64*kB))
+        self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
+        self.bus.add_region("sram", SoCRegion(
+                origin = self.bus.regions["psram"].origin + 0*kB,
+                size   = 64*kB,
+                linker = True)
+        )
         if not self.integrated_main_ram_size:
             self.bus.add_region("main_ram", SoCRegion(
-                origin = self.bus.regions["sram"].origin + 64*kB,
+                origin = self.bus.regions["psram"].origin + 64*kB,
                 size   = 64*kB,
                 linker = True)
             )