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vcu118/ddram: use similar IO settings than Xilinx's MIG, comment unus…
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…ed pins.
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@enjoy-digital
enjoy-digital committed Feb 26, 2020
1 parent 9d2ca50 commit e516ff3
Showing 1 changed file with 58 additions and 38 deletions.
96 changes: 58 additions & 38 deletions litex_boards/platforms/vcu118.py
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Original file line number Diff line number Diff line change
Expand Up @@ -69,20 +69,22 @@
Subsignal("a", Pins(
"D14 B15 B16 C14 C15 A13 A14 A15",
"A16 B12 C12 B13 C13 D15"),
IOStandard("SSTL12")),
Subsignal("ba", Pins("G15 G13"), IOStandard("SSTL12")),
Subsignal("bg", Pins("H13"), IOStandard("SSTL12")),
Subsignal("ras_n", Pins("F15"), IOStandard("SSTL12")),
Subsignal("cas_n", Pins("H15"), IOStandard("SSTL12")),
Subsignal("we_n", Pins("H14"), IOStandard("SSTL12")),
Subsignal("cs_n", Pins("F13"), IOStandard("SSTL12")),
Subsignal("act_n", Pins("E13"), IOStandard("SSTL12")),
Subsignal("ten", Pins("A20"), IOStandard("POD12")),
Subsignal("alert_n", Pins("R17"), IOStandard("POD12")),
Subsignal("par", Pins("G10"), IOStandard("POD12")),
IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("G15 G13"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("H13"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("F15"), IOStandard("SSTL12_DCI")), # A16
Subsignal("cas_n", Pins("H15"), IOStandard("SSTL12_DCI")), # A15
Subsignal("we_n", Pins("H14"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cs_n", Pins("F13"), IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("E13"), IOStandard("SSTL12_DCI")),
#Subsignal("ten", Pins("A20"), IOStandard("SSTL12_DCI")),
#Subsignal("alert_n", Pins("R17"), IOStandard("SSTL12_DCI")),
#Subsignal("par", Pins("G10"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins(
"G11 R18 K17 G18 B18 P20 L23 G22"),
IOStandard("POD12")),
IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dq", Pins(
"F11 E11 F10 F9 H12 G12 E9 D9",
"R19 P19 M18 M17 N19 N18 N17 M16",
Expand All @@ -92,35 +94,46 @@
"N23 M23 R21 P21 R22 P22 T23 R23",
"K24 J24 M21 L21 K21 J21 K22 J22",
"H23 H22 E23 E22 F21 E21 F24 F23"),
IOStandard("POD12")),
Subsignal("dqs_p", Pins("D11 P17 K19 F16 A19 N22 M20 H24"), IOStandard("DIFF_POD12")),
Subsignal("dqs_n", Pins("D10 P16 J19 E16 A18 M22 L20 G23"), IOStandard("DIFF_POD12")),
Subsignal("clk_p", Pins("F14"), IOStandard("DIFF_POD12")),
Subsignal("clk_n", Pins("E14"), IOStandard("DIFF_POD12")),
Subsignal("cke", Pins("A10"), IOStandard("SSTL12")),
Subsignal("odt", Pins("C8"), IOStandard("SSTL12")),
IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins("D11 P17 K19 F16 A19 N22 M20 H24"),
IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins("D10 P16 J19 E16 A18 M22 L20 G23"),
IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("clk_p", Pins("F14"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_n", Pins("E14"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cke", Pins("A10"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("C8"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("N20"), IOStandard("LVCMOS12")),
Misc("SLEW=FAST"),
),

# DDR4 memory channel C2.
("ddram_second_channel", 0,
Subsignal("a", Pins(
"AM27 AL27 AP26 AP25 AN28 AM28 AP28 AP27",
"AN26 AM26 AR28 AR27 AV25 AT25"),
IOStandard("SSTL12")),
Subsignal("ba", Pins("AR25 AU28"), IOStandard("SSTL12")),
Subsignal("bg", Pins("AU27"), IOStandard("SSTL12")),
Subsignal("ras_n", Pins("AV26"), IOStandard("SSTL12")),
Subsignal("cas_n", Pins("AU26"), IOStandard("SSTL12")),
Subsignal("we_n", Pins("AV28"), IOStandard("SSTL12")),
Subsignal("cs_n", Pins("AY29"), IOStandard("SSTL12")),
Subsignal("act_n", Pins("AN25"), IOStandard("SSTL12")),
Subsignal("ten", Pins("AY35"), IOStandard("POD12")),
Subsignal("alert_n", Pins("AR29"), IOStandard("SSTL12")),
Subsignal("par", Pins("BF29"), IOStandard("POD12")),
IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("AR25 AU28"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("AU27"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("AV26"), IOStandard("SSTL12_DCI")), # A16
Subsignal("cas_n", Pins("AU26"), IOStandard("SSTL12_DCI")), # A15
Subsignal("we_n", Pins("AV28"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cs_n", Pins("AY29"), IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("AN25"), IOStandard("SSTL12_DCI")),
#Subsignal("ten", Pins("AY35"), IOStandard("SSTL12_DCI")),
#Subsignal("alert_n", Pins("AR29"), IOStandard("SSTL12_DCI")),
#Subsignal("par", Pins("BF29"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins(
"BE32 BB31 AV33 AR32 BC34 BE40 AY37 AV35 BE29 BA29"),
IOStandard("SSTL12")),
IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dq", Pins(
"BD30 BE30 BD32 BE33 BC33 BD33 BC31 BD31",
"BA32 BB33 BA30 BA31 AW31 AW32 AY32 AY33",
Expand All @@ -132,18 +145,25 @@
"AW35 AW36 AU40 AV40 AU38 AU39 AV38 AV39",
"BF26 BF27 BD28 BE28 BD27 BE27 BD25 BD26",
"BC25 BC26 BB28 BC28 AY27 AY28 BA27 BB27"),
IOStandard("POD12")),
IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins(
"BF30 AY34 AU29 AP31 BE35 BE39 BA35 AW37 BE25 BA26"),
IOStandard("DIFF_POD12")),
IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins(
"BF31 BA34 AV29 AP32 BF35 BF39 BA36 AW38 BF25 BB26"),
IOStandard("DIFF_POD12")),
Subsignal("clk_p", Pins("AT26"), IOStandard("DIFF_POD12")),
Subsignal("clk_n", Pins("AT27"), IOStandard("DIFF_POD12")),
Subsignal("cke", Pins("AW28"), IOStandard("SSTL12")),
Subsignal("odt", Pins("BB29"), IOStandard("SSTL12")),
IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("clk_p", Pins("AT26"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_n", Pins("AT27"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cke", Pins("AW28"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("BB29"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("BD35"), IOStandard("LVCMOS12")),
Misc("SLEW=FAST"),
),
]

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