Add support for ZCU104 board #47
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litex_boards/targets/zcu104.py
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| self.add_csr("ddrphy") | ||
| self.add_constant("USDDRPHY", None) | ||
| # FIXME: Use correct DDR4 module | ||
| sdram_module = EDY4016A(sys_clk_freq, "1:4") |
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I did play with LiteX on the ZCU104 a while ago, never got round to something upstreamable in the end due to other priorities. But this DDR config worked daveshah1/litedram@f08cfe6#diff-bc9fdc9a0f1aa798161b2333f66733b7R450 and this was my board file https://github.com/daveshah1/litex-boards/blob/6d7eb0df09d7c886fa93b26f6d763dc78082408c/litex_boards/community/platforms/zcu104.py
litex_boards/targets/zcu104.py
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| ] | ||
| self.specials += [ | ||
| Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE", | ||
| i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset, |
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Although I didn't realise at the time and 200MHz worked fine; officially the UltraScale+ requires 300MHz minimum for IDELAYCTRLs, this may matter if pushing the DDR4 clock higher and needing finer delay control.
| return VivadoProgrammer() | ||
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| def do_finalize(self, fragment): | ||
| XilinxPlatform.do_finalize(self, fragment) |
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From memory, I needed these lines here for reliable DDR4:
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 65]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 66]")
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indeed, it will not work without it.
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@daveshah1 thanks for the links |
piotr-binkowski
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Thanks @piotr-binkowski for the PR, @daveshah1 for the feedback. I'll have a closer look for the minimum IDELAYCTRL frequency. @piotr-binkowski can you use similar IO settings than 9d2ca50? I just did some comparisons with the Xilinx's MIG and updated the settings. (The ZCU104 should use similar settings, but if you want to check, you can download the MIG example for the ZCU104 board and compare the IO settings between Xilinx's MIG and your desgin in the IO report .rpt file). |
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I will try to use the settings you mentioned, at the moment I've managed to get the LiteDRAM partially working - I can use only half of the data bus width because the other half seems to fail during read leveling phase. I've also modified the design to use 500MHz clock for IDELAYCTRL (I couldn't get 300MHz output to work with current PLL setup so I'm using 500MHz for now) |
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This now depends on enjoy-digital/litedram#154 |
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@piotr-binkowski: Do you want to merge it now and open an issue for the remaining things to look at or wait everything is fixed before merging? |
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@enjoy-digital I think we can merge it now and create an issue for the remaining things |
piotr-binkowski
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This adds basic support for the ZCU104 board, DDR4 configuration is currently untested.