[HWMemSimImpl] Fix RW port enable gating (#5700)

Co-authored-by: Nandor Licker <nandorl@sifive.com>
llvm · Jul 27, 2023 · 636d4a4 · 636d4a4
1 parent d89cdf0
commit 636d4a4
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Showing 2 changed files with 21 additions and 2 deletions.
diff --git a/lib/Dialect/SV/Transforms/HWMemSimImpl.cpp b/lib/Dialect/SV/Transforms/HWMemSimImpl.cpp
@@ -362,8 +362,11 @@ void HWMemSimImpl::generateMemory(HWModuleOp op, FirMemory mem) {
         false);
 
     auto val = getMemoryRead(b, reg, read_addr, addMuxPragmas);
-    Value x = b.create<sv::ConstantXOp>(val.getType());
-    b.create<sv::AssignOp>(rWire, b.create<comb::MuxOp>(rcond, val, x, false));
+    if (!ignoreReadEnable) {
+      Value x = b.create<sv::ConstantXOp>(val.getType());
+      val = b.create<comb::MuxOp>(rcond, val, x, false);
+    }
+    b.create<sv::AssignOp>(rWire, val);
 
     // Write logic gaurded by the corresponding mask bit.
     for (auto wmask : llvm::enumerate(maskValues)) {

diff --git a/test/Dialect/SV/hw-memsim.mlir b/test/Dialect/SV/hw-memsim.mlir
@@ -1,4 +1,5 @@
 // RUN: circt-opt -hw-memory-sim %s | FileCheck %s --check-prefix COMMON --implicit-check-not sv.attributes
+// RUN: circt-opt -pass-pipeline="builtin.module(hw-memory-sim{ignore-read-enable})" %s | FileCheck %s --check-prefixes=COMMON,IGNORE
 // RUN: circt-opt -pass-pipeline="builtin.module(hw-memory-sim{add-mux-pragmas})" %s | FileCheck %s --check-prefixes=COMMON,PRAMGAS
 // RUN: circt-opt -pass-pipeline="builtin.module(hw-memory-sim{disable-mem-randomization})" %s | FileCheck %s --check-prefix COMMON --implicit-check-not RANDOMIZE_MEM
 // RUN: circt-opt -pass-pipeline="builtin.module(hw-memory-sim{disable-reg-randomization})" %s | FileCheck %s --check-prefix COMMON --implicit-check-not RANDOMIZE_REG
@@ -137,6 +138,16 @@ hw.module.generated @FIRRTLMem_1_1_1_16_10_0_1_0_0, @FIRRTLMem(%ro_addr_0: i4, %
 //CHECK-NEXT:  }
 //CHECK-NEXT:  hw.output %[[readres]], %[[rwres]]
 
+// IGNORE: %[[Memory:.+]] = sv.reg : !hw.inout<uarray<10xi16>>
+// IGNORE: %[[ro_slot:.+]] = sv.array_index_inout %[[Memory]][%ro_addr_0] : !hw.inout<uarray<10xi16>>, i4
+// IGNORE: %[[result_ro:.+]] = sv.read_inout %[[ro_slot]] : !hw.inout<i16>
+// IGNORE: %[[rw_wire:.+]] = sv.wire : !hw.inout<i16>
+// IGNORE: %[[wire_slot:.+]] = sv.read_inout %2 : !hw.inout<i16>
+// IGNORE: %[[rw_slot:.+]] = sv.array_index_inout %[[Memory]][%rw_addr_0] : !hw.inout<uarray<10xi16>>, i4
+// IGNORE: %[[rw_value:.+]] = sv.read_inout %[[rw_slot]] : !hw.inout<i16>
+// IGNORE: sv.assign %[[rw_wire]], %[[rw_value]] : i16
+// IGNORE: hw.output %[[result_ro]], %[[wire_slot]] : i16, i16
+
 hw.module.generated @FIRRTLMem_1_1_1_16_10_2_4_0_0, @FIRRTLMem(%ro_addr_0: i4, %ro_en_0: i1, %ro_clock_0: i1,%rw_addr_0: i4, %rw_en_0: i1,  %rw_clock_0: i1, %rw_wmode_0: i1, %rw_wdata_0: i16, %wo_addr_0: i4, %wo_en_0: i1, %wo_clock_0: i1, %wo_data_0: i16) -> (ro_data_0: i16, rw_rdata_0: i16) attributes {depth = 10 : i64, numReadPorts = 1 : ui32, numReadWritePorts = 1 : ui32, numWritePorts = 1 : ui32, readLatency = 2 : ui32, readUnderWrite = 0 : i32, width = 16 : ui32, writeClockIDs = [], writeLatency = 4 : ui32, writeUnderWrite = 0 : i32, initFilename = "", initIsBinary = false, initIsInline = false}
 
 //COMMON-LABEL: @FIRRTLMem_1_1_1_16_10_2_4_0_0
@@ -206,6 +217,11 @@ hw.module.generated @FIRRTLMemTwoAlways, @FIRRTLMem( %wo_addr_0: i4, %wo_en_0: i
   // CHECK-NEXT:      %[[v220:.+]] = sv.indexed_part_select_inout %[[v26]][%[[c0_i32]] : 8] : !hw.inout<i32>, i32
   // CHECK-NEXT:      sv.passign %[[v220]], %[[v15]] : i8
 
+  // IGNORE:      %[[Memory:.+]] = sv.reg : !hw.inout<uarray<16xi32>>
+  // IGNORE:      %[[slot:.+]] = sv.array_index_inout %Memory
+  // IGNORE-NEXT: %[[result:.+]] = sv.read_inout %[[slot]]
+  // IGNORE:      hw.output %[[result]]
+
   hw.module.generated @FIRRTLMem_1_1_0_32_16_1_1_0_1_b, @FIRRTLMem(%R0_addr: i4, %R0_en: i1, %R0_clk: i1, %W0_addr: i4, %W0_en: i1, %W0_clk: i1, %W0_data: i32, %W0_mask: i2) -> (R0_data: i32) attributes {depth = 16 : i64, maskGran = 16 : ui32, numReadPorts = 1 : ui32, numReadWritePorts = 0 : ui32, numWritePorts = 1 : ui32, readLatency = 2 : ui32, readUnderWrite = 0 : i32, width = 32 : ui32, writeClockIDs = [0 : i32], writeLatency = 3 : ui32, writeUnderWrite = 1 : i32, initFilename = "", initIsBinary = false, initIsInline = false}
   hw.module @memTestBar(%clock: i1, %rAddr: i4, %rEn: i1, %wAddr: i4, %wEn: i1, %wMask: i2, %wData: i32) -> (rData: i32) attributes {firrtl.moduleHierarchyFile = #hw.output_file<"testharness_hier.json", excludeFromFileList>} {
     %memory.R0_data = hw.instance "memory" @FIRRTLMem_1_1_0_32_16_1_1_0_1_b(R0_addr: %rAddr: i4, R0_en: %rEn: i1,