[HWMemSimImpl] Fix RW port enable gating

[nandor]

No description provided.

[seldridge]

Needs a test. 😉

[uenoku]

LGTM

[seldridge]

The behavior here for a read-write port is not exactly the same as that for a read port. The output with this option (with this patch) is:

  reg [31:0] Memory[0:7];
  reg [2:0]  _GEN;
  always @(posedge R0_clk) begin
    if (R0_en)
      _GEN <= R0_addr;
  end // always @(posedge)
  reg [2:0]  _GEN_0;
  reg        _GEN_1;
  reg        _GEN_2;
  always @(posedge RW0_clk) begin
    _GEN_0 <= RW0_addr;
    _GEN_1 <= RW0_en;
    _GEN_2 <= RW0_wmode;
    if (RW0_en & RW0_wmode)
      Memory[RW0_addr] <= RW0_wdata;
  end // always @(posedge)
  assign R0_data = Memory[_GEN];
  assign RW0_rdata = Memory[_GEN_0];

The behavior here should be the same. I.e., this should return either the old address or just ignore the read enable. I'm inclined for the former as it still preserves the functionality of the read enable while the latter does not.

WDYT?

[seldridge]

I checked the old SFC behavior for this and this produces the following output:

  reg [31:0] memory [0:7];
  wire  memory_r_en;
  wire [2:0] memory_r_addr;
  wire [31:0] memory_r_data;
  wire  memory_rw_r_en;
  wire [2:0] memory_rw_r_addr;
  wire [31:0] memory_rw_r_data;
  wire [31:0] memory_rw_w_data;
  wire [2:0] memory_rw_w_addr;
  wire  memory_rw_w_mask;
  wire  memory_rw_w_en;
  reg  memory_r_en_pipe_0;
  reg [2:0] memory_r_addr_pipe_0;
  reg  memory_rw_r_en_pipe_0;
  reg [2:0] memory_rw_r_addr_pipe_0;
  assign memory_r_en = memory_r_en_pipe_0;
  assign memory_r_addr = memory_r_addr_pipe_0;
  assign memory_r_data = memory[memory_r_addr];
  assign memory_rw_r_en = memory_rw_r_en_pipe_0;
  assign memory_rw_r_addr = memory_rw_r_addr_pipe_0;
  assign memory_rw_r_data = memory[memory_rw_r_addr];
  assign memory_rw_w_data = rw_wdata;
  assign memory_rw_w_addr = rw_addr;
  assign memory_rw_w_mask = rw_wmask;
  assign memory_rw_w_en = rw_en & rw_wmode;
  assign r_data = memory_r_data;
  assign rw_rdata = memory_rw_r_data;
  always @(posedge rw_clk) begin
    if (memory_rw_w_en & memory_rw_w_mask) begin
      memory[memory_rw_w_addr] <= memory_rw_w_data;
    end
    memory_rw_r_en_pipe_0 <= rw_en & ~rw_wmode;
    if (rw_en & ~rw_wmode) begin
      memory_rw_r_addr_pipe_0 <= rw_addr;
    end
  end
  always @(posedge r_clk) begin
    memory_r_en_pipe_0 <= r_en;
    if (r_en) begin
      memory_r_addr_pipe_0 <= r_addr;
    end
  end

We should update this to do the same thing here.

[seldridge]

Fix to align things is here: #5704